stm32l4x2_pac/dbgmcu/
apb2fzr.rs

1#[doc = r" Value read from the register"]
2pub struct R {
3    bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7    bits: u32,
8}
9impl super::APB2FZR {
10    #[doc = r" Modifies the contents of the register"]
11    #[inline]
12    pub fn modify<F>(&self, f: F)
13    where
14        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15    {
16        let bits = self.register.get();
17        let r = R { bits: bits };
18        let mut w = W { bits: bits };
19        f(&r, &mut w);
20        self.register.set(w.bits);
21    }
22    #[doc = r" Reads the contents of the register"]
23    #[inline]
24    pub fn read(&self) -> R {
25        R {
26            bits: self.register.get(),
27        }
28    }
29    #[doc = r" Writes to the register"]
30    #[inline]
31    pub fn write<F>(&self, f: F)
32    where
33        F: FnOnce(&mut W) -> &mut W,
34    {
35        let mut w = W::reset_value();
36        f(&mut w);
37        self.register.set(w.bits);
38    }
39    #[doc = r" Writes the reset value to the register"]
40    #[inline]
41    pub fn reset(&self) {
42        self.write(|w| w)
43    }
44}
45#[doc = r" Value of the field"]
46pub struct DBG_TIM1_STOPR {
47    bits: bool,
48}
49impl DBG_TIM1_STOPR {
50    #[doc = r" Value of the field as raw bits"]
51    #[inline]
52    pub fn bit(&self) -> bool {
53        self.bits
54    }
55    #[doc = r" Returns `true` if the bit is clear (0)"]
56    #[inline]
57    pub fn bit_is_clear(&self) -> bool {
58        !self.bit()
59    }
60    #[doc = r" Returns `true` if the bit is set (1)"]
61    #[inline]
62    pub fn bit_is_set(&self) -> bool {
63        self.bit()
64    }
65}
66#[doc = r" Value of the field"]
67pub struct DBG_TIM15_STOPR {
68    bits: bool,
69}
70impl DBG_TIM15_STOPR {
71    #[doc = r" Value of the field as raw bits"]
72    #[inline]
73    pub fn bit(&self) -> bool {
74        self.bits
75    }
76    #[doc = r" Returns `true` if the bit is clear (0)"]
77    #[inline]
78    pub fn bit_is_clear(&self) -> bool {
79        !self.bit()
80    }
81    #[doc = r" Returns `true` if the bit is set (1)"]
82    #[inline]
83    pub fn bit_is_set(&self) -> bool {
84        self.bit()
85    }
86}
87#[doc = r" Value of the field"]
88pub struct DBG_TIM16_STOPR {
89    bits: bool,
90}
91impl DBG_TIM16_STOPR {
92    #[doc = r" Value of the field as raw bits"]
93    #[inline]
94    pub fn bit(&self) -> bool {
95        self.bits
96    }
97    #[doc = r" Returns `true` if the bit is clear (0)"]
98    #[inline]
99    pub fn bit_is_clear(&self) -> bool {
100        !self.bit()
101    }
102    #[doc = r" Returns `true` if the bit is set (1)"]
103    #[inline]
104    pub fn bit_is_set(&self) -> bool {
105        self.bit()
106    }
107}
108#[doc = r" Proxy"]
109pub struct _DBG_TIM1_STOPW<'a> {
110    w: &'a mut W,
111}
112impl<'a> _DBG_TIM1_STOPW<'a> {
113    #[doc = r" Sets the field bit"]
114    pub fn set_bit(self) -> &'a mut W {
115        self.bit(true)
116    }
117    #[doc = r" Clears the field bit"]
118    pub fn clear_bit(self) -> &'a mut W {
119        self.bit(false)
120    }
121    #[doc = r" Writes raw bits to the field"]
122    #[inline]
123    pub fn bit(self, value: bool) -> &'a mut W {
124        const MASK: bool = true;
125        const OFFSET: u8 = 11;
126        self.w.bits &= !((MASK as u32) << OFFSET);
127        self.w.bits |= ((value & MASK) as u32) << OFFSET;
128        self.w
129    }
130}
131#[doc = r" Proxy"]
132pub struct _DBG_TIM15_STOPW<'a> {
133    w: &'a mut W,
134}
135impl<'a> _DBG_TIM15_STOPW<'a> {
136    #[doc = r" Sets the field bit"]
137    pub fn set_bit(self) -> &'a mut W {
138        self.bit(true)
139    }
140    #[doc = r" Clears the field bit"]
141    pub fn clear_bit(self) -> &'a mut W {
142        self.bit(false)
143    }
144    #[doc = r" Writes raw bits to the field"]
145    #[inline]
146    pub fn bit(self, value: bool) -> &'a mut W {
147        const MASK: bool = true;
148        const OFFSET: u8 = 16;
149        self.w.bits &= !((MASK as u32) << OFFSET);
150        self.w.bits |= ((value & MASK) as u32) << OFFSET;
151        self.w
152    }
153}
154#[doc = r" Proxy"]
155pub struct _DBG_TIM16_STOPW<'a> {
156    w: &'a mut W,
157}
158impl<'a> _DBG_TIM16_STOPW<'a> {
159    #[doc = r" Sets the field bit"]
160    pub fn set_bit(self) -> &'a mut W {
161        self.bit(true)
162    }
163    #[doc = r" Clears the field bit"]
164    pub fn clear_bit(self) -> &'a mut W {
165        self.bit(false)
166    }
167    #[doc = r" Writes raw bits to the field"]
168    #[inline]
169    pub fn bit(self, value: bool) -> &'a mut W {
170        const MASK: bool = true;
171        const OFFSET: u8 = 17;
172        self.w.bits &= !((MASK as u32) << OFFSET);
173        self.w.bits |= ((value & MASK) as u32) << OFFSET;
174        self.w
175    }
176}
177impl R {
178    #[doc = r" Value of the register as raw bits"]
179    #[inline]
180    pub fn bits(&self) -> u32 {
181        self.bits
182    }
183    #[doc = "Bit 11 - TIM1 counter stopped when core is halted"]
184    #[inline]
185    pub fn dbg_tim1_stop(&self) -> DBG_TIM1_STOPR {
186        let bits = {
187            const MASK: bool = true;
188            const OFFSET: u8 = 11;
189            ((self.bits >> OFFSET) & MASK as u32) != 0
190        };
191        DBG_TIM1_STOPR { bits }
192    }
193    #[doc = "Bit 16 - TIM15 counter stopped when core is halted"]
194    #[inline]
195    pub fn dbg_tim15_stop(&self) -> DBG_TIM15_STOPR {
196        let bits = {
197            const MASK: bool = true;
198            const OFFSET: u8 = 16;
199            ((self.bits >> OFFSET) & MASK as u32) != 0
200        };
201        DBG_TIM15_STOPR { bits }
202    }
203    #[doc = "Bit 17 - TIM16 counter stopped when core is halted"]
204    #[inline]
205    pub fn dbg_tim16_stop(&self) -> DBG_TIM16_STOPR {
206        let bits = {
207            const MASK: bool = true;
208            const OFFSET: u8 = 17;
209            ((self.bits >> OFFSET) & MASK as u32) != 0
210        };
211        DBG_TIM16_STOPR { bits }
212    }
213}
214impl W {
215    #[doc = r" Reset value of the register"]
216    #[inline]
217    pub fn reset_value() -> W {
218        W { bits: 0 }
219    }
220    #[doc = r" Writes raw bits to the register"]
221    #[inline]
222    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
223        self.bits = bits;
224        self
225    }
226    #[doc = "Bit 11 - TIM1 counter stopped when core is halted"]
227    #[inline]
228    pub fn dbg_tim1_stop(&mut self) -> _DBG_TIM1_STOPW {
229        _DBG_TIM1_STOPW { w: self }
230    }
231    #[doc = "Bit 16 - TIM15 counter stopped when core is halted"]
232    #[inline]
233    pub fn dbg_tim15_stop(&mut self) -> _DBG_TIM15_STOPW {
234        _DBG_TIM15_STOPW { w: self }
235    }
236    #[doc = "Bit 17 - TIM16 counter stopped when core is halted"]
237    #[inline]
238    pub fn dbg_tim16_stop(&mut self) -> _DBG_TIM16_STOPW {
239        _DBG_TIM16_STOPW { w: self }
240    }
241}
stm32l4x2_pac/dbgmcu/apb2fzr.rs

stm32l4x2_pac/dbgmcu/
apb2fzr.rs
