stm32l4x2_pac/tim6/
egr.rs

1#[doc = r" Value to write to the register"]
2pub struct W {
3    bits: u32,
4}
5impl super::EGR {
6    #[doc = r" Writes to the register"]
7    #[inline]
8    pub fn write<F>(&self, f: F)
9    where
10        F: FnOnce(&mut W) -> &mut W,
11    {
12        let mut w = W::reset_value();
13        f(&mut w);
14        self.register.set(w.bits);
15    }
16}
17#[doc = "Values that can be written to the field `UG`"]
18pub enum UGW {
19    #[doc = "Re-initializes the timer counter and generates an update of the reigsters."]
20    UPDATE,
21}
22impl UGW {
23    #[allow(missing_docs)]
24    #[doc(hidden)]
25    #[inline]
26    pub fn _bits(&self) -> bool {
27        match *self {
28            UGW::UPDATE => true,
29        }
30    }
31}
32#[doc = r" Proxy"]
33pub struct _UGW<'a> {
34    w: &'a mut W,
35}
36impl<'a> _UGW<'a> {
37    #[doc = r" Writes `variant` to the field"]
38    #[inline]
39    pub fn variant(self, variant: UGW) -> &'a mut W {
40        {
41            self.bit(variant._bits())
42        }
43    }
44    #[doc = "Re-initializes the timer counter and generates an update of the reigsters."]
45    #[inline]
46    pub fn update(self) -> &'a mut W {
47        self.variant(UGW::UPDATE)
48    }
49    #[doc = r" Sets the field bit"]
50    pub fn set_bit(self) -> &'a mut W {
51        self.bit(true)
52    }
53    #[doc = r" Clears the field bit"]
54    pub fn clear_bit(self) -> &'a mut W {
55        self.bit(false)
56    }
57    #[doc = r" Writes raw bits to the field"]
58    #[inline]
59    pub fn bit(self, value: bool) -> &'a mut W {
60        const MASK: bool = true;
61        const OFFSET: u8 = 0;
62        self.w.bits &= !((MASK as u32) << OFFSET);
63        self.w.bits |= ((value & MASK) as u32) << OFFSET;
64        self.w
65    }
66}
67impl W {
68    #[doc = r" Reset value of the register"]
69    #[inline]
70    pub fn reset_value() -> W {
71        W { bits: 0 }
72    }
73    #[doc = r" Writes raw bits to the register"]
74    #[inline]
75    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
76        self.bits = bits;
77        self
78    }
79    #[doc = "Bit 0 - Update generation"]
80    #[inline]
81    pub fn ug(&mut self) -> _UGW {
82        _UGW { w: self }
83    }
84}
stm32l4x2_pac/tim6/egr.rs

stm32l4x2_pac/tim6/
egr.rs
