1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::CR1 {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = "Possible values of the field `ARPE`"]
46#[derive(Clone, Copy, Debug, PartialEq)]
47pub enum ARPER {
48 #[doc = "TIMx_APRR register is not buffered"]
49 DISABLED,
50 #[doc = "TIMx_APRR register is buffered"]
51 ENABLED,
52}
53impl ARPER {
54 #[doc = r" Returns `true` if the bit is clear (0)"]
55 #[inline]
56 pub fn bit_is_clear(&self) -> bool {
57 !self.bit()
58 }
59 #[doc = r" Returns `true` if the bit is set (1)"]
60 #[inline]
61 pub fn bit_is_set(&self) -> bool {
62 self.bit()
63 }
64 #[doc = r" Value of the field as raw bits"]
65 #[inline]
66 pub fn bit(&self) -> bool {
67 match *self {
68 ARPER::DISABLED => false,
69 ARPER::ENABLED => true,
70 }
71 }
72 #[allow(missing_docs)]
73 #[doc(hidden)]
74 #[inline]
75 pub fn _from(value: bool) -> ARPER {
76 match value {
77 false => ARPER::DISABLED,
78 true => ARPER::ENABLED,
79 }
80 }
81 #[doc = "Checks if the value of the field is `DISABLED`"]
82 #[inline]
83 pub fn is_disabled(&self) -> bool {
84 *self == ARPER::DISABLED
85 }
86 #[doc = "Checks if the value of the field is `ENABLED`"]
87 #[inline]
88 pub fn is_enabled(&self) -> bool {
89 *self == ARPER::ENABLED
90 }
91}
92#[doc = "Possible values of the field `OPM`"]
93#[derive(Clone, Copy, Debug, PartialEq)]
94pub enum OPMR {
95 #[doc = "Counter is not stopped at update event"]
96 DISABLED,
97 #[doc = "Counter stops counting at the next update event (clearing the CEN bit)"]
98 ENABLED,
99}
100impl OPMR {
101 #[doc = r" Returns `true` if the bit is clear (0)"]
102 #[inline]
103 pub fn bit_is_clear(&self) -> bool {
104 !self.bit()
105 }
106 #[doc = r" Returns `true` if the bit is set (1)"]
107 #[inline]
108 pub fn bit_is_set(&self) -> bool {
109 self.bit()
110 }
111 #[doc = r" Value of the field as raw bits"]
112 #[inline]
113 pub fn bit(&self) -> bool {
114 match *self {
115 OPMR::DISABLED => false,
116 OPMR::ENABLED => true,
117 }
118 }
119 #[allow(missing_docs)]
120 #[doc(hidden)]
121 #[inline]
122 pub fn _from(value: bool) -> OPMR {
123 match value {
124 false => OPMR::DISABLED,
125 true => OPMR::ENABLED,
126 }
127 }
128 #[doc = "Checks if the value of the field is `DISABLED`"]
129 #[inline]
130 pub fn is_disabled(&self) -> bool {
131 *self == OPMR::DISABLED
132 }
133 #[doc = "Checks if the value of the field is `ENABLED`"]
134 #[inline]
135 pub fn is_enabled(&self) -> bool {
136 *self == OPMR::ENABLED
137 }
138}
139#[doc = "Possible values of the field `URS`"]
140#[derive(Clone, Copy, Debug, PartialEq)]
141pub enum URSR {
142 #[doc = "Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request"]
143 ANYEVENT,
144 #[doc = "Only counter overflow/underflow generates an update interrupt or DMA request"]
145 COUNTERONLY,
146}
147impl URSR {
148 #[doc = r" Returns `true` if the bit is clear (0)"]
149 #[inline]
150 pub fn bit_is_clear(&self) -> bool {
151 !self.bit()
152 }
153 #[doc = r" Returns `true` if the bit is set (1)"]
154 #[inline]
155 pub fn bit_is_set(&self) -> bool {
156 self.bit()
157 }
158 #[doc = r" Value of the field as raw bits"]
159 #[inline]
160 pub fn bit(&self) -> bool {
161 match *self {
162 URSR::ANYEVENT => false,
163 URSR::COUNTERONLY => true,
164 }
165 }
166 #[allow(missing_docs)]
167 #[doc(hidden)]
168 #[inline]
169 pub fn _from(value: bool) -> URSR {
170 match value {
171 false => URSR::ANYEVENT,
172 true => URSR::COUNTERONLY,
173 }
174 }
175 #[doc = "Checks if the value of the field is `ANYEVENT`"]
176 #[inline]
177 pub fn is_any_event(&self) -> bool {
178 *self == URSR::ANYEVENT
179 }
180 #[doc = "Checks if the value of the field is `COUNTERONLY`"]
181 #[inline]
182 pub fn is_counter_only(&self) -> bool {
183 *self == URSR::COUNTERONLY
184 }
185}
186#[doc = "Possible values of the field `UDIS`"]
187#[derive(Clone, Copy, Debug, PartialEq)]
188pub enum UDISR {
189 #[doc = "Update event enabled"]
190 ENABLED,
191 #[doc = "Update event disabled"]
192 DISABLED,
193}
194impl UDISR {
195 #[doc = r" Returns `true` if the bit is clear (0)"]
196 #[inline]
197 pub fn bit_is_clear(&self) -> bool {
198 !self.bit()
199 }
200 #[doc = r" Returns `true` if the bit is set (1)"]
201 #[inline]
202 pub fn bit_is_set(&self) -> bool {
203 self.bit()
204 }
205 #[doc = r" Value of the field as raw bits"]
206 #[inline]
207 pub fn bit(&self) -> bool {
208 match *self {
209 UDISR::ENABLED => false,
210 UDISR::DISABLED => true,
211 }
212 }
213 #[allow(missing_docs)]
214 #[doc(hidden)]
215 #[inline]
216 pub fn _from(value: bool) -> UDISR {
217 match value {
218 false => UDISR::ENABLED,
219 true => UDISR::DISABLED,
220 }
221 }
222 #[doc = "Checks if the value of the field is `ENABLED`"]
223 #[inline]
224 pub fn is_enabled(&self) -> bool {
225 *self == UDISR::ENABLED
226 }
227 #[doc = "Checks if the value of the field is `DISABLED`"]
228 #[inline]
229 pub fn is_disabled(&self) -> bool {
230 *self == UDISR::DISABLED
231 }
232}
233#[doc = "Possible values of the field `CEN`"]
234#[derive(Clone, Copy, Debug, PartialEq)]
235pub enum CENR {
236 #[doc = "Counter disabled"]
237 DISABLED,
238 #[doc = "Counter enabled"]
239 ENABLED,
240}
241impl CENR {
242 #[doc = r" Returns `true` if the bit is clear (0)"]
243 #[inline]
244 pub fn bit_is_clear(&self) -> bool {
245 !self.bit()
246 }
247 #[doc = r" Returns `true` if the bit is set (1)"]
248 #[inline]
249 pub fn bit_is_set(&self) -> bool {
250 self.bit()
251 }
252 #[doc = r" Value of the field as raw bits"]
253 #[inline]
254 pub fn bit(&self) -> bool {
255 match *self {
256 CENR::DISABLED => false,
257 CENR::ENABLED => true,
258 }
259 }
260 #[allow(missing_docs)]
261 #[doc(hidden)]
262 #[inline]
263 pub fn _from(value: bool) -> CENR {
264 match value {
265 false => CENR::DISABLED,
266 true => CENR::ENABLED,
267 }
268 }
269 #[doc = "Checks if the value of the field is `DISABLED`"]
270 #[inline]
271 pub fn is_disabled(&self) -> bool {
272 *self == CENR::DISABLED
273 }
274 #[doc = "Checks if the value of the field is `ENABLED`"]
275 #[inline]
276 pub fn is_enabled(&self) -> bool {
277 *self == CENR::ENABLED
278 }
279}
280#[doc = "Values that can be written to the field `ARPE`"]
281pub enum ARPEW {
282 #[doc = "TIMx_APRR register is not buffered"]
283 DISABLED,
284 #[doc = "TIMx_APRR register is buffered"]
285 ENABLED,
286}
287impl ARPEW {
288 #[allow(missing_docs)]
289 #[doc(hidden)]
290 #[inline]
291 pub fn _bits(&self) -> bool {
292 match *self {
293 ARPEW::DISABLED => false,
294 ARPEW::ENABLED => true,
295 }
296 }
297}
298#[doc = r" Proxy"]
299pub struct _ARPEW<'a> {
300 w: &'a mut W,
301}
302impl<'a> _ARPEW<'a> {
303 #[doc = r" Writes `variant` to the field"]
304 #[inline]
305 pub fn variant(self, variant: ARPEW) -> &'a mut W {
306 {
307 self.bit(variant._bits())
308 }
309 }
310 #[doc = "TIMx_APRR register is not buffered"]
311 #[inline]
312 pub fn disabled(self) -> &'a mut W {
313 self.variant(ARPEW::DISABLED)
314 }
315 #[doc = "TIMx_APRR register is buffered"]
316 #[inline]
317 pub fn enabled(self) -> &'a mut W {
318 self.variant(ARPEW::ENABLED)
319 }
320 #[doc = r" Sets the field bit"]
321 pub fn set_bit(self) -> &'a mut W {
322 self.bit(true)
323 }
324 #[doc = r" Clears the field bit"]
325 pub fn clear_bit(self) -> &'a mut W {
326 self.bit(false)
327 }
328 #[doc = r" Writes raw bits to the field"]
329 #[inline]
330 pub fn bit(self, value: bool) -> &'a mut W {
331 const MASK: bool = true;
332 const OFFSET: u8 = 7;
333 self.w.bits &= !((MASK as u32) << OFFSET);
334 self.w.bits |= ((value & MASK) as u32) << OFFSET;
335 self.w
336 }
337}
338#[doc = "Values that can be written to the field `OPM`"]
339pub enum OPMW {
340 #[doc = "Counter is not stopped at update event"]
341 DISABLED,
342 #[doc = "Counter stops counting at the next update event (clearing the CEN bit)"]
343 ENABLED,
344}
345impl OPMW {
346 #[allow(missing_docs)]
347 #[doc(hidden)]
348 #[inline]
349 pub fn _bits(&self) -> bool {
350 match *self {
351 OPMW::DISABLED => false,
352 OPMW::ENABLED => true,
353 }
354 }
355}
356#[doc = r" Proxy"]
357pub struct _OPMW<'a> {
358 w: &'a mut W,
359}
360impl<'a> _OPMW<'a> {
361 #[doc = r" Writes `variant` to the field"]
362 #[inline]
363 pub fn variant(self, variant: OPMW) -> &'a mut W {
364 {
365 self.bit(variant._bits())
366 }
367 }
368 #[doc = "Counter is not stopped at update event"]
369 #[inline]
370 pub fn disabled(self) -> &'a mut W {
371 self.variant(OPMW::DISABLED)
372 }
373 #[doc = "Counter stops counting at the next update event (clearing the CEN bit)"]
374 #[inline]
375 pub fn enabled(self) -> &'a mut W {
376 self.variant(OPMW::ENABLED)
377 }
378 #[doc = r" Sets the field bit"]
379 pub fn set_bit(self) -> &'a mut W {
380 self.bit(true)
381 }
382 #[doc = r" Clears the field bit"]
383 pub fn clear_bit(self) -> &'a mut W {
384 self.bit(false)
385 }
386 #[doc = r" Writes raw bits to the field"]
387 #[inline]
388 pub fn bit(self, value: bool) -> &'a mut W {
389 const MASK: bool = true;
390 const OFFSET: u8 = 3;
391 self.w.bits &= !((MASK as u32) << OFFSET);
392 self.w.bits |= ((value & MASK) as u32) << OFFSET;
393 self.w
394 }
395}
396#[doc = "Values that can be written to the field `URS`"]
397pub enum URSW {
398 #[doc = "Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request"]
399 ANYEVENT,
400 #[doc = "Only counter overflow/underflow generates an update interrupt or DMA request"]
401 COUNTERONLY,
402}
403impl URSW {
404 #[allow(missing_docs)]
405 #[doc(hidden)]
406 #[inline]
407 pub fn _bits(&self) -> bool {
408 match *self {
409 URSW::ANYEVENT => false,
410 URSW::COUNTERONLY => true,
411 }
412 }
413}
414#[doc = r" Proxy"]
415pub struct _URSW<'a> {
416 w: &'a mut W,
417}
418impl<'a> _URSW<'a> {
419 #[doc = r" Writes `variant` to the field"]
420 #[inline]
421 pub fn variant(self, variant: URSW) -> &'a mut W {
422 {
423 self.bit(variant._bits())
424 }
425 }
426 #[doc = "Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request"]
427 #[inline]
428 pub fn any_event(self) -> &'a mut W {
429 self.variant(URSW::ANYEVENT)
430 }
431 #[doc = "Only counter overflow/underflow generates an update interrupt or DMA request"]
432 #[inline]
433 pub fn counter_only(self) -> &'a mut W {
434 self.variant(URSW::COUNTERONLY)
435 }
436 #[doc = r" Sets the field bit"]
437 pub fn set_bit(self) -> &'a mut W {
438 self.bit(true)
439 }
440 #[doc = r" Clears the field bit"]
441 pub fn clear_bit(self) -> &'a mut W {
442 self.bit(false)
443 }
444 #[doc = r" Writes raw bits to the field"]
445 #[inline]
446 pub fn bit(self, value: bool) -> &'a mut W {
447 const MASK: bool = true;
448 const OFFSET: u8 = 2;
449 self.w.bits &= !((MASK as u32) << OFFSET);
450 self.w.bits |= ((value & MASK) as u32) << OFFSET;
451 self.w
452 }
453}
454#[doc = "Values that can be written to the field `UDIS`"]
455pub enum UDISW {
456 #[doc = "Update event enabled"]
457 ENABLED,
458 #[doc = "Update event disabled"]
459 DISABLED,
460}
461impl UDISW {
462 #[allow(missing_docs)]
463 #[doc(hidden)]
464 #[inline]
465 pub fn _bits(&self) -> bool {
466 match *self {
467 UDISW::ENABLED => false,
468 UDISW::DISABLED => true,
469 }
470 }
471}
472#[doc = r" Proxy"]
473pub struct _UDISW<'a> {
474 w: &'a mut W,
475}
476impl<'a> _UDISW<'a> {
477 #[doc = r" Writes `variant` to the field"]
478 #[inline]
479 pub fn variant(self, variant: UDISW) -> &'a mut W {
480 {
481 self.bit(variant._bits())
482 }
483 }
484 #[doc = "Update event enabled"]
485 #[inline]
486 pub fn enabled(self) -> &'a mut W {
487 self.variant(UDISW::ENABLED)
488 }
489 #[doc = "Update event disabled"]
490 #[inline]
491 pub fn disabled(self) -> &'a mut W {
492 self.variant(UDISW::DISABLED)
493 }
494 #[doc = r" Sets the field bit"]
495 pub fn set_bit(self) -> &'a mut W {
496 self.bit(true)
497 }
498 #[doc = r" Clears the field bit"]
499 pub fn clear_bit(self) -> &'a mut W {
500 self.bit(false)
501 }
502 #[doc = r" Writes raw bits to the field"]
503 #[inline]
504 pub fn bit(self, value: bool) -> &'a mut W {
505 const MASK: bool = true;
506 const OFFSET: u8 = 1;
507 self.w.bits &= !((MASK as u32) << OFFSET);
508 self.w.bits |= ((value & MASK) as u32) << OFFSET;
509 self.w
510 }
511}
512#[doc = "Values that can be written to the field `CEN`"]
513pub enum CENW {
514 #[doc = "Counter disabled"]
515 DISABLED,
516 #[doc = "Counter enabled"]
517 ENABLED,
518}
519impl CENW {
520 #[allow(missing_docs)]
521 #[doc(hidden)]
522 #[inline]
523 pub fn _bits(&self) -> bool {
524 match *self {
525 CENW::DISABLED => false,
526 CENW::ENABLED => true,
527 }
528 }
529}
530#[doc = r" Proxy"]
531pub struct _CENW<'a> {
532 w: &'a mut W,
533}
534impl<'a> _CENW<'a> {
535 #[doc = r" Writes `variant` to the field"]
536 #[inline]
537 pub fn variant(self, variant: CENW) -> &'a mut W {
538 {
539 self.bit(variant._bits())
540 }
541 }
542 #[doc = "Counter disabled"]
543 #[inline]
544 pub fn disabled(self) -> &'a mut W {
545 self.variant(CENW::DISABLED)
546 }
547 #[doc = "Counter enabled"]
548 #[inline]
549 pub fn enabled(self) -> &'a mut W {
550 self.variant(CENW::ENABLED)
551 }
552 #[doc = r" Sets the field bit"]
553 pub fn set_bit(self) -> &'a mut W {
554 self.bit(true)
555 }
556 #[doc = r" Clears the field bit"]
557 pub fn clear_bit(self) -> &'a mut W {
558 self.bit(false)
559 }
560 #[doc = r" Writes raw bits to the field"]
561 #[inline]
562 pub fn bit(self, value: bool) -> &'a mut W {
563 const MASK: bool = true;
564 const OFFSET: u8 = 0;
565 self.w.bits &= !((MASK as u32) << OFFSET);
566 self.w.bits |= ((value & MASK) as u32) << OFFSET;
567 self.w
568 }
569}
570impl R {
571 #[doc = r" Value of the register as raw bits"]
572 #[inline]
573 pub fn bits(&self) -> u32 {
574 self.bits
575 }
576 #[doc = "Bit 7 - Auto-reload preload enable"]
577 #[inline]
578 pub fn arpe(&self) -> ARPER {
579 ARPER::_from({
580 const MASK: bool = true;
581 const OFFSET: u8 = 7;
582 ((self.bits >> OFFSET) & MASK as u32) != 0
583 })
584 }
585 #[doc = "Bit 3 - One-pulse mode"]
586 #[inline]
587 pub fn opm(&self) -> OPMR {
588 OPMR::_from({
589 const MASK: bool = true;
590 const OFFSET: u8 = 3;
591 ((self.bits >> OFFSET) & MASK as u32) != 0
592 })
593 }
594 #[doc = "Bit 2 - Update request source"]
595 #[inline]
596 pub fn urs(&self) -> URSR {
597 URSR::_from({
598 const MASK: bool = true;
599 const OFFSET: u8 = 2;
600 ((self.bits >> OFFSET) & MASK as u32) != 0
601 })
602 }
603 #[doc = "Bit 1 - Update disable"]
604 #[inline]
605 pub fn udis(&self) -> UDISR {
606 UDISR::_from({
607 const MASK: bool = true;
608 const OFFSET: u8 = 1;
609 ((self.bits >> OFFSET) & MASK as u32) != 0
610 })
611 }
612 #[doc = "Bit 0 - Counter enable"]
613 #[inline]
614 pub fn cen(&self) -> CENR {
615 CENR::_from({
616 const MASK: bool = true;
617 const OFFSET: u8 = 0;
618 ((self.bits >> OFFSET) & MASK as u32) != 0
619 })
620 }
621}
622impl W {
623 #[doc = r" Reset value of the register"]
624 #[inline]
625 pub fn reset_value() -> W {
626 W { bits: 0 }
627 }
628 #[doc = r" Writes raw bits to the register"]
629 #[inline]
630 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
631 self.bits = bits;
632 self
633 }
634 #[doc = "Bit 7 - Auto-reload preload enable"]
635 #[inline]
636 pub fn arpe(&mut self) -> _ARPEW {
637 _ARPEW { w: self }
638 }
639 #[doc = "Bit 3 - One-pulse mode"]
640 #[inline]
641 pub fn opm(&mut self) -> _OPMW {
642 _OPMW { w: self }
643 }
644 #[doc = "Bit 2 - Update request source"]
645 #[inline]
646 pub fn urs(&mut self) -> _URSW {
647 _URSW { w: self }
648 }
649 #[doc = "Bit 1 - Update disable"]
650 #[inline]
651 pub fn udis(&mut self) -> _UDISW {
652 _UDISW { w: self }
653 }
654 #[doc = "Bit 0 - Counter enable"]
655 #[inline]
656 pub fn cen(&mut self) -> _CENW {
657 _CENW { w: self }
658 }
659}