stm32l4x2_pac/tim16/
egr.rs

1#[doc = r" Value to write to the register"]
2pub struct W {
3    bits: u32,
4}
5impl super::EGR {
6    #[doc = r" Writes to the register"]
7    #[inline]
8    pub fn write<F>(&self, f: F)
9    where
10        F: FnOnce(&mut W) -> &mut W,
11    {
12        let mut w = W::reset_value();
13        f(&mut w);
14        self.register.set(w.bits);
15    }
16}
17#[doc = r" Proxy"]
18pub struct _BGW<'a> {
19    w: &'a mut W,
20}
21impl<'a> _BGW<'a> {
22    #[doc = r" Sets the field bit"]
23    pub fn set_bit(self) -> &'a mut W {
24        self.bit(true)
25    }
26    #[doc = r" Clears the field bit"]
27    pub fn clear_bit(self) -> &'a mut W {
28        self.bit(false)
29    }
30    #[doc = r" Writes raw bits to the field"]
31    #[inline]
32    pub fn bit(self, value: bool) -> &'a mut W {
33        const MASK: bool = true;
34        const OFFSET: u8 = 7;
35        self.w.bits &= !((MASK as u32) << OFFSET);
36        self.w.bits |= ((value & MASK) as u32) << OFFSET;
37        self.w
38    }
39}
40#[doc = r" Proxy"]
41pub struct _TGW<'a> {
42    w: &'a mut W,
43}
44impl<'a> _TGW<'a> {
45    #[doc = r" Sets the field bit"]
46    pub fn set_bit(self) -> &'a mut W {
47        self.bit(true)
48    }
49    #[doc = r" Clears the field bit"]
50    pub fn clear_bit(self) -> &'a mut W {
51        self.bit(false)
52    }
53    #[doc = r" Writes raw bits to the field"]
54    #[inline]
55    pub fn bit(self, value: bool) -> &'a mut W {
56        const MASK: bool = true;
57        const OFFSET: u8 = 6;
58        self.w.bits &= !((MASK as u32) << OFFSET);
59        self.w.bits |= ((value & MASK) as u32) << OFFSET;
60        self.w
61    }
62}
63#[doc = r" Proxy"]
64pub struct _COMGW<'a> {
65    w: &'a mut W,
66}
67impl<'a> _COMGW<'a> {
68    #[doc = r" Sets the field bit"]
69    pub fn set_bit(self) -> &'a mut W {
70        self.bit(true)
71    }
72    #[doc = r" Clears the field bit"]
73    pub fn clear_bit(self) -> &'a mut W {
74        self.bit(false)
75    }
76    #[doc = r" Writes raw bits to the field"]
77    #[inline]
78    pub fn bit(self, value: bool) -> &'a mut W {
79        const MASK: bool = true;
80        const OFFSET: u8 = 5;
81        self.w.bits &= !((MASK as u32) << OFFSET);
82        self.w.bits |= ((value & MASK) as u32) << OFFSET;
83        self.w
84    }
85}
86#[doc = r" Proxy"]
87pub struct _CC1GW<'a> {
88    w: &'a mut W,
89}
90impl<'a> _CC1GW<'a> {
91    #[doc = r" Sets the field bit"]
92    pub fn set_bit(self) -> &'a mut W {
93        self.bit(true)
94    }
95    #[doc = r" Clears the field bit"]
96    pub fn clear_bit(self) -> &'a mut W {
97        self.bit(false)
98    }
99    #[doc = r" Writes raw bits to the field"]
100    #[inline]
101    pub fn bit(self, value: bool) -> &'a mut W {
102        const MASK: bool = true;
103        const OFFSET: u8 = 1;
104        self.w.bits &= !((MASK as u32) << OFFSET);
105        self.w.bits |= ((value & MASK) as u32) << OFFSET;
106        self.w
107    }
108}
109#[doc = "Values that can be written to the field `UG`"]
110pub enum UGW {
111    #[doc = "Re-initializes the timer counter and generates an update of the reigsters."]
112    UPDATE,
113}
114impl UGW {
115    #[allow(missing_docs)]
116    #[doc(hidden)]
117    #[inline]
118    pub fn _bits(&self) -> bool {
119        match *self {
120            UGW::UPDATE => true,
121        }
122    }
123}
124#[doc = r" Proxy"]
125pub struct _UGW<'a> {
126    w: &'a mut W,
127}
128impl<'a> _UGW<'a> {
129    #[doc = r" Writes `variant` to the field"]
130    #[inline]
131    pub fn variant(self, variant: UGW) -> &'a mut W {
132        {
133            self.bit(variant._bits())
134        }
135    }
136    #[doc = "Re-initializes the timer counter and generates an update of the reigsters."]
137    #[inline]
138    pub fn update(self) -> &'a mut W {
139        self.variant(UGW::UPDATE)
140    }
141    #[doc = r" Sets the field bit"]
142    pub fn set_bit(self) -> &'a mut W {
143        self.bit(true)
144    }
145    #[doc = r" Clears the field bit"]
146    pub fn clear_bit(self) -> &'a mut W {
147        self.bit(false)
148    }
149    #[doc = r" Writes raw bits to the field"]
150    #[inline]
151    pub fn bit(self, value: bool) -> &'a mut W {
152        const MASK: bool = true;
153        const OFFSET: u8 = 0;
154        self.w.bits &= !((MASK as u32) << OFFSET);
155        self.w.bits |= ((value & MASK) as u32) << OFFSET;
156        self.w
157    }
158}
159impl W {
160    #[doc = r" Reset value of the register"]
161    #[inline]
162    pub fn reset_value() -> W {
163        W { bits: 0 }
164    }
165    #[doc = r" Writes raw bits to the register"]
166    #[inline]
167    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
168        self.bits = bits;
169        self
170    }
171    #[doc = "Bit 7 - Break generation"]
172    #[inline]
173    pub fn bg(&mut self) -> _BGW {
174        _BGW { w: self }
175    }
176    #[doc = "Bit 6 - Trigger generation"]
177    #[inline]
178    pub fn tg(&mut self) -> _TGW {
179        _TGW { w: self }
180    }
181    #[doc = "Bit 5 - Capture/Compare control update generation"]
182    #[inline]
183    pub fn comg(&mut self) -> _COMGW {
184        _COMGW { w: self }
185    }
186    #[doc = "Bit 1 - Capture/compare 1 generation"]
187    #[inline]
188    pub fn cc1g(&mut self) -> _CC1GW {
189        _CC1GW { w: self }
190    }
191    #[doc = "Bit 0 - Update generation"]
192    #[inline]
193    pub fn ug(&mut self) -> _UGW {
194        _UGW { w: self }
195    }
196}
stm32l4x2_pac/tim16/egr.rs

stm32l4x2_pac/tim16/
egr.rs
