1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::CR1 {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = "Possible values of the field `CEN`"]
46#[derive(Clone, Copy, Debug, PartialEq)]
47pub enum CENR {
48 #[doc = "Counter disabled"]
49 DISABLED,
50 #[doc = "Counter enabled"]
51 ENABLED,
52}
53impl CENR {
54 #[doc = r" Returns `true` if the bit is clear (0)"]
55 #[inline]
56 pub fn bit_is_clear(&self) -> bool {
57 !self.bit()
58 }
59 #[doc = r" Returns `true` if the bit is set (1)"]
60 #[inline]
61 pub fn bit_is_set(&self) -> bool {
62 self.bit()
63 }
64 #[doc = r" Value of the field as raw bits"]
65 #[inline]
66 pub fn bit(&self) -> bool {
67 match *self {
68 CENR::DISABLED => false,
69 CENR::ENABLED => true,
70 }
71 }
72 #[allow(missing_docs)]
73 #[doc(hidden)]
74 #[inline]
75 pub fn _from(value: bool) -> CENR {
76 match value {
77 false => CENR::DISABLED,
78 true => CENR::ENABLED,
79 }
80 }
81 #[doc = "Checks if the value of the field is `DISABLED`"]
82 #[inline]
83 pub fn is_disabled(&self) -> bool {
84 *self == CENR::DISABLED
85 }
86 #[doc = "Checks if the value of the field is `ENABLED`"]
87 #[inline]
88 pub fn is_enabled(&self) -> bool {
89 *self == CENR::ENABLED
90 }
91}
92#[doc = "Possible values of the field `UDIS`"]
93#[derive(Clone, Copy, Debug, PartialEq)]
94pub enum UDISR {
95 #[doc = "Update event enabled"]
96 ENABLED,
97 #[doc = "Update event disabled"]
98 DISABLED,
99}
100impl UDISR {
101 #[doc = r" Returns `true` if the bit is clear (0)"]
102 #[inline]
103 pub fn bit_is_clear(&self) -> bool {
104 !self.bit()
105 }
106 #[doc = r" Returns `true` if the bit is set (1)"]
107 #[inline]
108 pub fn bit_is_set(&self) -> bool {
109 self.bit()
110 }
111 #[doc = r" Value of the field as raw bits"]
112 #[inline]
113 pub fn bit(&self) -> bool {
114 match *self {
115 UDISR::ENABLED => false,
116 UDISR::DISABLED => true,
117 }
118 }
119 #[allow(missing_docs)]
120 #[doc(hidden)]
121 #[inline]
122 pub fn _from(value: bool) -> UDISR {
123 match value {
124 false => UDISR::ENABLED,
125 true => UDISR::DISABLED,
126 }
127 }
128 #[doc = "Checks if the value of the field is `ENABLED`"]
129 #[inline]
130 pub fn is_enabled(&self) -> bool {
131 *self == UDISR::ENABLED
132 }
133 #[doc = "Checks if the value of the field is `DISABLED`"]
134 #[inline]
135 pub fn is_disabled(&self) -> bool {
136 *self == UDISR::DISABLED
137 }
138}
139#[doc = "Possible values of the field `URS`"]
140#[derive(Clone, Copy, Debug, PartialEq)]
141pub enum URSR {
142 #[doc = "Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request"]
143 ANYEVENT,
144 #[doc = "Only counter overflow/underflow generates an update interrupt or DMA request"]
145 COUNTERONLY,
146}
147impl URSR {
148 #[doc = r" Returns `true` if the bit is clear (0)"]
149 #[inline]
150 pub fn bit_is_clear(&self) -> bool {
151 !self.bit()
152 }
153 #[doc = r" Returns `true` if the bit is set (1)"]
154 #[inline]
155 pub fn bit_is_set(&self) -> bool {
156 self.bit()
157 }
158 #[doc = r" Value of the field as raw bits"]
159 #[inline]
160 pub fn bit(&self) -> bool {
161 match *self {
162 URSR::ANYEVENT => false,
163 URSR::COUNTERONLY => true,
164 }
165 }
166 #[allow(missing_docs)]
167 #[doc(hidden)]
168 #[inline]
169 pub fn _from(value: bool) -> URSR {
170 match value {
171 false => URSR::ANYEVENT,
172 true => URSR::COUNTERONLY,
173 }
174 }
175 #[doc = "Checks if the value of the field is `ANYEVENT`"]
176 #[inline]
177 pub fn is_any_event(&self) -> bool {
178 *self == URSR::ANYEVENT
179 }
180 #[doc = "Checks if the value of the field is `COUNTERONLY`"]
181 #[inline]
182 pub fn is_counter_only(&self) -> bool {
183 *self == URSR::COUNTERONLY
184 }
185}
186#[doc = "Possible values of the field `OPM`"]
187#[derive(Clone, Copy, Debug, PartialEq)]
188pub enum OPMR {
189 #[doc = "Not stopped at update event"]
190 NOTSTOPPED,
191 #[doc = "Counter stops counting at next update event"]
192 STOPPED,
193}
194impl OPMR {
195 #[doc = r" Returns `true` if the bit is clear (0)"]
196 #[inline]
197 pub fn bit_is_clear(&self) -> bool {
198 !self.bit()
199 }
200 #[doc = r" Returns `true` if the bit is set (1)"]
201 #[inline]
202 pub fn bit_is_set(&self) -> bool {
203 self.bit()
204 }
205 #[doc = r" Value of the field as raw bits"]
206 #[inline]
207 pub fn bit(&self) -> bool {
208 match *self {
209 OPMR::NOTSTOPPED => false,
210 OPMR::STOPPED => true,
211 }
212 }
213 #[allow(missing_docs)]
214 #[doc(hidden)]
215 #[inline]
216 pub fn _from(value: bool) -> OPMR {
217 match value {
218 false => OPMR::NOTSTOPPED,
219 true => OPMR::STOPPED,
220 }
221 }
222 #[doc = "Checks if the value of the field is `NOTSTOPPED`"]
223 #[inline]
224 pub fn is_not_stopped(&self) -> bool {
225 *self == OPMR::NOTSTOPPED
226 }
227 #[doc = "Checks if the value of the field is `STOPPED`"]
228 #[inline]
229 pub fn is_stopped(&self) -> bool {
230 *self == OPMR::STOPPED
231 }
232}
233#[doc = "Possible values of the field `ARPE`"]
234#[derive(Clone, Copy, Debug, PartialEq)]
235pub enum ARPER {
236 #[doc = "TIMx_APRR register is not buffered"]
237 DISABLED,
238 #[doc = "TIMx_APRR register is buffered"]
239 ENABLED,
240}
241impl ARPER {
242 #[doc = r" Returns `true` if the bit is clear (0)"]
243 #[inline]
244 pub fn bit_is_clear(&self) -> bool {
245 !self.bit()
246 }
247 #[doc = r" Returns `true` if the bit is set (1)"]
248 #[inline]
249 pub fn bit_is_set(&self) -> bool {
250 self.bit()
251 }
252 #[doc = r" Value of the field as raw bits"]
253 #[inline]
254 pub fn bit(&self) -> bool {
255 match *self {
256 ARPER::DISABLED => false,
257 ARPER::ENABLED => true,
258 }
259 }
260 #[allow(missing_docs)]
261 #[doc(hidden)]
262 #[inline]
263 pub fn _from(value: bool) -> ARPER {
264 match value {
265 false => ARPER::DISABLED,
266 true => ARPER::ENABLED,
267 }
268 }
269 #[doc = "Checks if the value of the field is `DISABLED`"]
270 #[inline]
271 pub fn is_disabled(&self) -> bool {
272 *self == ARPER::DISABLED
273 }
274 #[doc = "Checks if the value of the field is `ENABLED`"]
275 #[inline]
276 pub fn is_enabled(&self) -> bool {
277 *self == ARPER::ENABLED
278 }
279}
280#[doc = r" Value of the field"]
281pub struct CKDR {
282 bits: u8,
283}
284impl CKDR {
285 #[doc = r" Value of the field as raw bits"]
286 #[inline]
287 pub fn bits(&self) -> u8 {
288 self.bits
289 }
290}
291#[doc = r" Value of the field"]
292pub struct UIFREMAPR {
293 bits: bool,
294}
295impl UIFREMAPR {
296 #[doc = r" Value of the field as raw bits"]
297 #[inline]
298 pub fn bit(&self) -> bool {
299 self.bits
300 }
301 #[doc = r" Returns `true` if the bit is clear (0)"]
302 #[inline]
303 pub fn bit_is_clear(&self) -> bool {
304 !self.bit()
305 }
306 #[doc = r" Returns `true` if the bit is set (1)"]
307 #[inline]
308 pub fn bit_is_set(&self) -> bool {
309 self.bit()
310 }
311}
312#[doc = "Values that can be written to the field `CEN`"]
313pub enum CENW {
314 #[doc = "Counter disabled"]
315 DISABLED,
316 #[doc = "Counter enabled"]
317 ENABLED,
318}
319impl CENW {
320 #[allow(missing_docs)]
321 #[doc(hidden)]
322 #[inline]
323 pub fn _bits(&self) -> bool {
324 match *self {
325 CENW::DISABLED => false,
326 CENW::ENABLED => true,
327 }
328 }
329}
330#[doc = r" Proxy"]
331pub struct _CENW<'a> {
332 w: &'a mut W,
333}
334impl<'a> _CENW<'a> {
335 #[doc = r" Writes `variant` to the field"]
336 #[inline]
337 pub fn variant(self, variant: CENW) -> &'a mut W {
338 {
339 self.bit(variant._bits())
340 }
341 }
342 #[doc = "Counter disabled"]
343 #[inline]
344 pub fn disabled(self) -> &'a mut W {
345 self.variant(CENW::DISABLED)
346 }
347 #[doc = "Counter enabled"]
348 #[inline]
349 pub fn enabled(self) -> &'a mut W {
350 self.variant(CENW::ENABLED)
351 }
352 #[doc = r" Sets the field bit"]
353 pub fn set_bit(self) -> &'a mut W {
354 self.bit(true)
355 }
356 #[doc = r" Clears the field bit"]
357 pub fn clear_bit(self) -> &'a mut W {
358 self.bit(false)
359 }
360 #[doc = r" Writes raw bits to the field"]
361 #[inline]
362 pub fn bit(self, value: bool) -> &'a mut W {
363 const MASK: bool = true;
364 const OFFSET: u8 = 0;
365 self.w.bits &= !((MASK as u32) << OFFSET);
366 self.w.bits |= ((value & MASK) as u32) << OFFSET;
367 self.w
368 }
369}
370#[doc = "Values that can be written to the field `UDIS`"]
371pub enum UDISW {
372 #[doc = "Update event enabled"]
373 ENABLED,
374 #[doc = "Update event disabled"]
375 DISABLED,
376}
377impl UDISW {
378 #[allow(missing_docs)]
379 #[doc(hidden)]
380 #[inline]
381 pub fn _bits(&self) -> bool {
382 match *self {
383 UDISW::ENABLED => false,
384 UDISW::DISABLED => true,
385 }
386 }
387}
388#[doc = r" Proxy"]
389pub struct _UDISW<'a> {
390 w: &'a mut W,
391}
392impl<'a> _UDISW<'a> {
393 #[doc = r" Writes `variant` to the field"]
394 #[inline]
395 pub fn variant(self, variant: UDISW) -> &'a mut W {
396 {
397 self.bit(variant._bits())
398 }
399 }
400 #[doc = "Update event enabled"]
401 #[inline]
402 pub fn enabled(self) -> &'a mut W {
403 self.variant(UDISW::ENABLED)
404 }
405 #[doc = "Update event disabled"]
406 #[inline]
407 pub fn disabled(self) -> &'a mut W {
408 self.variant(UDISW::DISABLED)
409 }
410 #[doc = r" Sets the field bit"]
411 pub fn set_bit(self) -> &'a mut W {
412 self.bit(true)
413 }
414 #[doc = r" Clears the field bit"]
415 pub fn clear_bit(self) -> &'a mut W {
416 self.bit(false)
417 }
418 #[doc = r" Writes raw bits to the field"]
419 #[inline]
420 pub fn bit(self, value: bool) -> &'a mut W {
421 const MASK: bool = true;
422 const OFFSET: u8 = 1;
423 self.w.bits &= !((MASK as u32) << OFFSET);
424 self.w.bits |= ((value & MASK) as u32) << OFFSET;
425 self.w
426 }
427}
428#[doc = "Values that can be written to the field `URS`"]
429pub enum URSW {
430 #[doc = "Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request"]
431 ANYEVENT,
432 #[doc = "Only counter overflow/underflow generates an update interrupt or DMA request"]
433 COUNTERONLY,
434}
435impl URSW {
436 #[allow(missing_docs)]
437 #[doc(hidden)]
438 #[inline]
439 pub fn _bits(&self) -> bool {
440 match *self {
441 URSW::ANYEVENT => false,
442 URSW::COUNTERONLY => true,
443 }
444 }
445}
446#[doc = r" Proxy"]
447pub struct _URSW<'a> {
448 w: &'a mut W,
449}
450impl<'a> _URSW<'a> {
451 #[doc = r" Writes `variant` to the field"]
452 #[inline]
453 pub fn variant(self, variant: URSW) -> &'a mut W {
454 {
455 self.bit(variant._bits())
456 }
457 }
458 #[doc = "Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request"]
459 #[inline]
460 pub fn any_event(self) -> &'a mut W {
461 self.variant(URSW::ANYEVENT)
462 }
463 #[doc = "Only counter overflow/underflow generates an update interrupt or DMA request"]
464 #[inline]
465 pub fn counter_only(self) -> &'a mut W {
466 self.variant(URSW::COUNTERONLY)
467 }
468 #[doc = r" Sets the field bit"]
469 pub fn set_bit(self) -> &'a mut W {
470 self.bit(true)
471 }
472 #[doc = r" Clears the field bit"]
473 pub fn clear_bit(self) -> &'a mut W {
474 self.bit(false)
475 }
476 #[doc = r" Writes raw bits to the field"]
477 #[inline]
478 pub fn bit(self, value: bool) -> &'a mut W {
479 const MASK: bool = true;
480 const OFFSET: u8 = 2;
481 self.w.bits &= !((MASK as u32) << OFFSET);
482 self.w.bits |= ((value & MASK) as u32) << OFFSET;
483 self.w
484 }
485}
486#[doc = "Values that can be written to the field `OPM`"]
487pub enum OPMW {
488 #[doc = "Not stopped at update event"]
489 NOTSTOPPED,
490 #[doc = "Counter stops counting at next update event"]
491 STOPPED,
492}
493impl OPMW {
494 #[allow(missing_docs)]
495 #[doc(hidden)]
496 #[inline]
497 pub fn _bits(&self) -> bool {
498 match *self {
499 OPMW::NOTSTOPPED => false,
500 OPMW::STOPPED => true,
501 }
502 }
503}
504#[doc = r" Proxy"]
505pub struct _OPMW<'a> {
506 w: &'a mut W,
507}
508impl<'a> _OPMW<'a> {
509 #[doc = r" Writes `variant` to the field"]
510 #[inline]
511 pub fn variant(self, variant: OPMW) -> &'a mut W {
512 {
513 self.bit(variant._bits())
514 }
515 }
516 #[doc = "Not stopped at update event"]
517 #[inline]
518 pub fn not_stopped(self) -> &'a mut W {
519 self.variant(OPMW::NOTSTOPPED)
520 }
521 #[doc = "Counter stops counting at next update event"]
522 #[inline]
523 pub fn stopped(self) -> &'a mut W {
524 self.variant(OPMW::STOPPED)
525 }
526 #[doc = r" Sets the field bit"]
527 pub fn set_bit(self) -> &'a mut W {
528 self.bit(true)
529 }
530 #[doc = r" Clears the field bit"]
531 pub fn clear_bit(self) -> &'a mut W {
532 self.bit(false)
533 }
534 #[doc = r" Writes raw bits to the field"]
535 #[inline]
536 pub fn bit(self, value: bool) -> &'a mut W {
537 const MASK: bool = true;
538 const OFFSET: u8 = 3;
539 self.w.bits &= !((MASK as u32) << OFFSET);
540 self.w.bits |= ((value & MASK) as u32) << OFFSET;
541 self.w
542 }
543}
544#[doc = "Values that can be written to the field `ARPE`"]
545pub enum ARPEW {
546 #[doc = "TIMx_APRR register is not buffered"]
547 DISABLED,
548 #[doc = "TIMx_APRR register is buffered"]
549 ENABLED,
550}
551impl ARPEW {
552 #[allow(missing_docs)]
553 #[doc(hidden)]
554 #[inline]
555 pub fn _bits(&self) -> bool {
556 match *self {
557 ARPEW::DISABLED => false,
558 ARPEW::ENABLED => true,
559 }
560 }
561}
562#[doc = r" Proxy"]
563pub struct _ARPEW<'a> {
564 w: &'a mut W,
565}
566impl<'a> _ARPEW<'a> {
567 #[doc = r" Writes `variant` to the field"]
568 #[inline]
569 pub fn variant(self, variant: ARPEW) -> &'a mut W {
570 {
571 self.bit(variant._bits())
572 }
573 }
574 #[doc = "TIMx_APRR register is not buffered"]
575 #[inline]
576 pub fn disabled(self) -> &'a mut W {
577 self.variant(ARPEW::DISABLED)
578 }
579 #[doc = "TIMx_APRR register is buffered"]
580 #[inline]
581 pub fn enabled(self) -> &'a mut W {
582 self.variant(ARPEW::ENABLED)
583 }
584 #[doc = r" Sets the field bit"]
585 pub fn set_bit(self) -> &'a mut W {
586 self.bit(true)
587 }
588 #[doc = r" Clears the field bit"]
589 pub fn clear_bit(self) -> &'a mut W {
590 self.bit(false)
591 }
592 #[doc = r" Writes raw bits to the field"]
593 #[inline]
594 pub fn bit(self, value: bool) -> &'a mut W {
595 const MASK: bool = true;
596 const OFFSET: u8 = 7;
597 self.w.bits &= !((MASK as u32) << OFFSET);
598 self.w.bits |= ((value & MASK) as u32) << OFFSET;
599 self.w
600 }
601}
602#[doc = r" Proxy"]
603pub struct _CKDW<'a> {
604 w: &'a mut W,
605}
606impl<'a> _CKDW<'a> {
607 #[doc = r" Writes raw bits to the field"]
608 #[inline]
609 pub unsafe fn bits(self, value: u8) -> &'a mut W {
610 const MASK: u8 = 3;
611 const OFFSET: u8 = 8;
612 self.w.bits &= !((MASK as u32) << OFFSET);
613 self.w.bits |= ((value & MASK) as u32) << OFFSET;
614 self.w
615 }
616}
617#[doc = r" Proxy"]
618pub struct _UIFREMAPW<'a> {
619 w: &'a mut W,
620}
621impl<'a> _UIFREMAPW<'a> {
622 #[doc = r" Sets the field bit"]
623 pub fn set_bit(self) -> &'a mut W {
624 self.bit(true)
625 }
626 #[doc = r" Clears the field bit"]
627 pub fn clear_bit(self) -> &'a mut W {
628 self.bit(false)
629 }
630 #[doc = r" Writes raw bits to the field"]
631 #[inline]
632 pub fn bit(self, value: bool) -> &'a mut W {
633 const MASK: bool = true;
634 const OFFSET: u8 = 11;
635 self.w.bits &= !((MASK as u32) << OFFSET);
636 self.w.bits |= ((value & MASK) as u32) << OFFSET;
637 self.w
638 }
639}
640impl R {
641 #[doc = r" Value of the register as raw bits"]
642 #[inline]
643 pub fn bits(&self) -> u32 {
644 self.bits
645 }
646 #[doc = "Bit 0 - Counter enable"]
647 #[inline]
648 pub fn cen(&self) -> CENR {
649 CENR::_from({
650 const MASK: bool = true;
651 const OFFSET: u8 = 0;
652 ((self.bits >> OFFSET) & MASK as u32) != 0
653 })
654 }
655 #[doc = "Bit 1 - Update disable"]
656 #[inline]
657 pub fn udis(&self) -> UDISR {
658 UDISR::_from({
659 const MASK: bool = true;
660 const OFFSET: u8 = 1;
661 ((self.bits >> OFFSET) & MASK as u32) != 0
662 })
663 }
664 #[doc = "Bit 2 - Update request source"]
665 #[inline]
666 pub fn urs(&self) -> URSR {
667 URSR::_from({
668 const MASK: bool = true;
669 const OFFSET: u8 = 2;
670 ((self.bits >> OFFSET) & MASK as u32) != 0
671 })
672 }
673 #[doc = "Bit 3 - One-pulse mode"]
674 #[inline]
675 pub fn opm(&self) -> OPMR {
676 OPMR::_from({
677 const MASK: bool = true;
678 const OFFSET: u8 = 3;
679 ((self.bits >> OFFSET) & MASK as u32) != 0
680 })
681 }
682 #[doc = "Bit 7 - Auto-reload preload enable"]
683 #[inline]
684 pub fn arpe(&self) -> ARPER {
685 ARPER::_from({
686 const MASK: bool = true;
687 const OFFSET: u8 = 7;
688 ((self.bits >> OFFSET) & MASK as u32) != 0
689 })
690 }
691 #[doc = "Bits 8:9 - Clock division"]
692 #[inline]
693 pub fn ckd(&self) -> CKDR {
694 let bits = {
695 const MASK: u8 = 3;
696 const OFFSET: u8 = 8;
697 ((self.bits >> OFFSET) & MASK as u32) as u8
698 };
699 CKDR { bits }
700 }
701 #[doc = "Bit 11 - UIF status bit remapping"]
702 #[inline]
703 pub fn uifremap(&self) -> UIFREMAPR {
704 let bits = {
705 const MASK: bool = true;
706 const OFFSET: u8 = 11;
707 ((self.bits >> OFFSET) & MASK as u32) != 0
708 };
709 UIFREMAPR { bits }
710 }
711}
712impl W {
713 #[doc = r" Reset value of the register"]
714 #[inline]
715 pub fn reset_value() -> W {
716 W { bits: 0 }
717 }
718 #[doc = r" Writes raw bits to the register"]
719 #[inline]
720 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
721 self.bits = bits;
722 self
723 }
724 #[doc = "Bit 0 - Counter enable"]
725 #[inline]
726 pub fn cen(&mut self) -> _CENW {
727 _CENW { w: self }
728 }
729 #[doc = "Bit 1 - Update disable"]
730 #[inline]
731 pub fn udis(&mut self) -> _UDISW {
732 _UDISW { w: self }
733 }
734 #[doc = "Bit 2 - Update request source"]
735 #[inline]
736 pub fn urs(&mut self) -> _URSW {
737 _URSW { w: self }
738 }
739 #[doc = "Bit 3 - One-pulse mode"]
740 #[inline]
741 pub fn opm(&mut self) -> _OPMW {
742 _OPMW { w: self }
743 }
744 #[doc = "Bit 7 - Auto-reload preload enable"]
745 #[inline]
746 pub fn arpe(&mut self) -> _ARPEW {
747 _ARPEW { w: self }
748 }
749 #[doc = "Bits 8:9 - Clock division"]
750 #[inline]
751 pub fn ckd(&mut self) -> _CKDW {
752 _CKDW { w: self }
753 }
754 #[doc = "Bit 11 - UIF status bit remapping"]
755 #[inline]
756 pub fn uifremap(&mut self) -> _UIFREMAPW {
757 _UIFREMAPW { w: self }
758 }
759}