stm32l4x2_pac/can1/rx/
rdtr.rs

1#[doc = r" Value read from the register"]
2pub struct R {
3    bits: u32,
4}
5impl super::RDTR {
6    #[doc = r" Reads the contents of the register"]
7    #[inline]
8    pub fn read(&self) -> R {
9        R {
10            bits: self.register.get(),
11        }
12    }
13}
14#[doc = r" Value of the field"]
15pub struct TIMER {
16    bits: u16,
17}
18impl TIMER {
19    #[doc = r" Value of the field as raw bits"]
20    #[inline]
21    pub fn bits(&self) -> u16 {
22        self.bits
23    }
24}
25#[doc = r" Value of the field"]
26pub struct FMIR {
27    bits: u8,
28}
29impl FMIR {
30    #[doc = r" Value of the field as raw bits"]
31    #[inline]
32    pub fn bits(&self) -> u8 {
33        self.bits
34    }
35}
36#[doc = r" Value of the field"]
37pub struct DLCR {
38    bits: u8,
39}
40impl DLCR {
41    #[doc = r" Value of the field as raw bits"]
42    #[inline]
43    pub fn bits(&self) -> u8 {
44        self.bits
45    }
46}
47impl R {
48    #[doc = r" Value of the register as raw bits"]
49    #[inline]
50    pub fn bits(&self) -> u32 {
51        self.bits
52    }
53    #[doc = "Bits 16:31 - TIME"]
54    #[inline]
55    pub fn time(&self) -> TIMER {
56        let bits = {
57            const MASK: u16 = 65535;
58            const OFFSET: u8 = 16;
59            ((self.bits >> OFFSET) & MASK as u32) as u16
60        };
61        TIMER { bits }
62    }
63    #[doc = "Bits 8:15 - FMI"]
64    #[inline]
65    pub fn fmi(&self) -> FMIR {
66        let bits = {
67            const MASK: u8 = 255;
68            const OFFSET: u8 = 8;
69            ((self.bits >> OFFSET) & MASK as u32) as u8
70        };
71        FMIR { bits }
72    }
73    #[doc = "Bits 0:3 - DLC"]
74    #[inline]
75    pub fn dlc(&self) -> DLCR {
76        let bits = {
77            const MASK: u8 = 15;
78            const OFFSET: u8 = 0;
79            ((self.bits >> OFFSET) & MASK as u32) as u8
80        };
81        DLCR { bits }
82    }
83}
stm32l4x2_pac/can1/rx/rdtr.rs

stm32l4x2_pac/can1/rx/
rdtr.rs
