1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::CR1 {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = "Possible values of the field `CEN`"]
46#[derive(Clone, Copy, Debug, PartialEq)]
47pub enum CENR {
48 #[doc = "Counter disabled"]
49 DISABLED,
50 #[doc = "Counter enabled"]
51 ENABLED,
52}
53impl CENR {
54 #[doc = r" Returns `true` if the bit is clear (0)"]
55 #[inline]
56 pub fn bit_is_clear(&self) -> bool {
57 !self.bit()
58 }
59 #[doc = r" Returns `true` if the bit is set (1)"]
60 #[inline]
61 pub fn bit_is_set(&self) -> bool {
62 self.bit()
63 }
64 #[doc = r" Value of the field as raw bits"]
65 #[inline]
66 pub fn bit(&self) -> bool {
67 match *self {
68 CENR::DISABLED => false,
69 CENR::ENABLED => true,
70 }
71 }
72 #[allow(missing_docs)]
73 #[doc(hidden)]
74 #[inline]
75 pub fn _from(value: bool) -> CENR {
76 match value {
77 false => CENR::DISABLED,
78 true => CENR::ENABLED,
79 }
80 }
81 #[doc = "Checks if the value of the field is `DISABLED`"]
82 #[inline]
83 pub fn is_disabled(&self) -> bool {
84 *self == CENR::DISABLED
85 }
86 #[doc = "Checks if the value of the field is `ENABLED`"]
87 #[inline]
88 pub fn is_enabled(&self) -> bool {
89 *self == CENR::ENABLED
90 }
91}
92#[doc = "Possible values of the field `UDIS`"]
93#[derive(Clone, Copy, Debug, PartialEq)]
94pub enum UDISR {
95 #[doc = "Update event enabled"]
96 ENABLED,
97 #[doc = "Update event disabled"]
98 DISABLED,
99}
100impl UDISR {
101 #[doc = r" Returns `true` if the bit is clear (0)"]
102 #[inline]
103 pub fn bit_is_clear(&self) -> bool {
104 !self.bit()
105 }
106 #[doc = r" Returns `true` if the bit is set (1)"]
107 #[inline]
108 pub fn bit_is_set(&self) -> bool {
109 self.bit()
110 }
111 #[doc = r" Value of the field as raw bits"]
112 #[inline]
113 pub fn bit(&self) -> bool {
114 match *self {
115 UDISR::ENABLED => false,
116 UDISR::DISABLED => true,
117 }
118 }
119 #[allow(missing_docs)]
120 #[doc(hidden)]
121 #[inline]
122 pub fn _from(value: bool) -> UDISR {
123 match value {
124 false => UDISR::ENABLED,
125 true => UDISR::DISABLED,
126 }
127 }
128 #[doc = "Checks if the value of the field is `ENABLED`"]
129 #[inline]
130 pub fn is_enabled(&self) -> bool {
131 *self == UDISR::ENABLED
132 }
133 #[doc = "Checks if the value of the field is `DISABLED`"]
134 #[inline]
135 pub fn is_disabled(&self) -> bool {
136 *self == UDISR::DISABLED
137 }
138}
139#[doc = "Possible values of the field `URS`"]
140#[derive(Clone, Copy, Debug, PartialEq)]
141pub enum URSR {
142 #[doc = "Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request"]
143 ANYEVENT,
144 #[doc = "Only counter overflow/underflow generates an update interrupt or DMA request"]
145 COUNTERONLY,
146}
147impl URSR {
148 #[doc = r" Returns `true` if the bit is clear (0)"]
149 #[inline]
150 pub fn bit_is_clear(&self) -> bool {
151 !self.bit()
152 }
153 #[doc = r" Returns `true` if the bit is set (1)"]
154 #[inline]
155 pub fn bit_is_set(&self) -> bool {
156 self.bit()
157 }
158 #[doc = r" Value of the field as raw bits"]
159 #[inline]
160 pub fn bit(&self) -> bool {
161 match *self {
162 URSR::ANYEVENT => false,
163 URSR::COUNTERONLY => true,
164 }
165 }
166 #[allow(missing_docs)]
167 #[doc(hidden)]
168 #[inline]
169 pub fn _from(value: bool) -> URSR {
170 match value {
171 false => URSR::ANYEVENT,
172 true => URSR::COUNTERONLY,
173 }
174 }
175 #[doc = "Checks if the value of the field is `ANYEVENT`"]
176 #[inline]
177 pub fn is_any_event(&self) -> bool {
178 *self == URSR::ANYEVENT
179 }
180 #[doc = "Checks if the value of the field is `COUNTERONLY`"]
181 #[inline]
182 pub fn is_counter_only(&self) -> bool {
183 *self == URSR::COUNTERONLY
184 }
185}
186#[doc = r" Value of the field"]
187pub struct OPMR {
188 bits: bool,
189}
190impl OPMR {
191 #[doc = r" Value of the field as raw bits"]
192 #[inline]
193 pub fn bit(&self) -> bool {
194 self.bits
195 }
196 #[doc = r" Returns `true` if the bit is clear (0)"]
197 #[inline]
198 pub fn bit_is_clear(&self) -> bool {
199 !self.bit()
200 }
201 #[doc = r" Returns `true` if the bit is set (1)"]
202 #[inline]
203 pub fn bit_is_set(&self) -> bool {
204 self.bit()
205 }
206}
207#[doc = "Possible values of the field `ARPE`"]
208#[derive(Clone, Copy, Debug, PartialEq)]
209pub enum ARPER {
210 #[doc = "TIMx_APRR register is not buffered"]
211 DISABLED,
212 #[doc = "TIMx_APRR register is buffered"]
213 ENABLED,
214}
215impl ARPER {
216 #[doc = r" Returns `true` if the bit is clear (0)"]
217 #[inline]
218 pub fn bit_is_clear(&self) -> bool {
219 !self.bit()
220 }
221 #[doc = r" Returns `true` if the bit is set (1)"]
222 #[inline]
223 pub fn bit_is_set(&self) -> bool {
224 self.bit()
225 }
226 #[doc = r" Value of the field as raw bits"]
227 #[inline]
228 pub fn bit(&self) -> bool {
229 match *self {
230 ARPER::DISABLED => false,
231 ARPER::ENABLED => true,
232 }
233 }
234 #[allow(missing_docs)]
235 #[doc(hidden)]
236 #[inline]
237 pub fn _from(value: bool) -> ARPER {
238 match value {
239 false => ARPER::DISABLED,
240 true => ARPER::ENABLED,
241 }
242 }
243 #[doc = "Checks if the value of the field is `DISABLED`"]
244 #[inline]
245 pub fn is_disabled(&self) -> bool {
246 *self == ARPER::DISABLED
247 }
248 #[doc = "Checks if the value of the field is `ENABLED`"]
249 #[inline]
250 pub fn is_enabled(&self) -> bool {
251 *self == ARPER::ENABLED
252 }
253}
254#[doc = r" Value of the field"]
255pub struct CKDR {
256 bits: u8,
257}
258impl CKDR {
259 #[doc = r" Value of the field as raw bits"]
260 #[inline]
261 pub fn bits(&self) -> u8 {
262 self.bits
263 }
264}
265#[doc = r" Value of the field"]
266pub struct UIFREMAPR {
267 bits: bool,
268}
269impl UIFREMAPR {
270 #[doc = r" Value of the field as raw bits"]
271 #[inline]
272 pub fn bit(&self) -> bool {
273 self.bits
274 }
275 #[doc = r" Returns `true` if the bit is clear (0)"]
276 #[inline]
277 pub fn bit_is_clear(&self) -> bool {
278 !self.bit()
279 }
280 #[doc = r" Returns `true` if the bit is set (1)"]
281 #[inline]
282 pub fn bit_is_set(&self) -> bool {
283 self.bit()
284 }
285}
286#[doc = "Values that can be written to the field `CEN`"]
287pub enum CENW {
288 #[doc = "Counter disabled"]
289 DISABLED,
290 #[doc = "Counter enabled"]
291 ENABLED,
292}
293impl CENW {
294 #[allow(missing_docs)]
295 #[doc(hidden)]
296 #[inline]
297 pub fn _bits(&self) -> bool {
298 match *self {
299 CENW::DISABLED => false,
300 CENW::ENABLED => true,
301 }
302 }
303}
304#[doc = r" Proxy"]
305pub struct _CENW<'a> {
306 w: &'a mut W,
307}
308impl<'a> _CENW<'a> {
309 #[doc = r" Writes `variant` to the field"]
310 #[inline]
311 pub fn variant(self, variant: CENW) -> &'a mut W {
312 {
313 self.bit(variant._bits())
314 }
315 }
316 #[doc = "Counter disabled"]
317 #[inline]
318 pub fn disabled(self) -> &'a mut W {
319 self.variant(CENW::DISABLED)
320 }
321 #[doc = "Counter enabled"]
322 #[inline]
323 pub fn enabled(self) -> &'a mut W {
324 self.variant(CENW::ENABLED)
325 }
326 #[doc = r" Sets the field bit"]
327 pub fn set_bit(self) -> &'a mut W {
328 self.bit(true)
329 }
330 #[doc = r" Clears the field bit"]
331 pub fn clear_bit(self) -> &'a mut W {
332 self.bit(false)
333 }
334 #[doc = r" Writes raw bits to the field"]
335 #[inline]
336 pub fn bit(self, value: bool) -> &'a mut W {
337 const MASK: bool = true;
338 const OFFSET: u8 = 0;
339 self.w.bits &= !((MASK as u32) << OFFSET);
340 self.w.bits |= ((value & MASK) as u32) << OFFSET;
341 self.w
342 }
343}
344#[doc = "Values that can be written to the field `UDIS`"]
345pub enum UDISW {
346 #[doc = "Update event enabled"]
347 ENABLED,
348 #[doc = "Update event disabled"]
349 DISABLED,
350}
351impl UDISW {
352 #[allow(missing_docs)]
353 #[doc(hidden)]
354 #[inline]
355 pub fn _bits(&self) -> bool {
356 match *self {
357 UDISW::ENABLED => false,
358 UDISW::DISABLED => true,
359 }
360 }
361}
362#[doc = r" Proxy"]
363pub struct _UDISW<'a> {
364 w: &'a mut W,
365}
366impl<'a> _UDISW<'a> {
367 #[doc = r" Writes `variant` to the field"]
368 #[inline]
369 pub fn variant(self, variant: UDISW) -> &'a mut W {
370 {
371 self.bit(variant._bits())
372 }
373 }
374 #[doc = "Update event enabled"]
375 #[inline]
376 pub fn enabled(self) -> &'a mut W {
377 self.variant(UDISW::ENABLED)
378 }
379 #[doc = "Update event disabled"]
380 #[inline]
381 pub fn disabled(self) -> &'a mut W {
382 self.variant(UDISW::DISABLED)
383 }
384 #[doc = r" Sets the field bit"]
385 pub fn set_bit(self) -> &'a mut W {
386 self.bit(true)
387 }
388 #[doc = r" Clears the field bit"]
389 pub fn clear_bit(self) -> &'a mut W {
390 self.bit(false)
391 }
392 #[doc = r" Writes raw bits to the field"]
393 #[inline]
394 pub fn bit(self, value: bool) -> &'a mut W {
395 const MASK: bool = true;
396 const OFFSET: u8 = 1;
397 self.w.bits &= !((MASK as u32) << OFFSET);
398 self.w.bits |= ((value & MASK) as u32) << OFFSET;
399 self.w
400 }
401}
402#[doc = "Values that can be written to the field `URS`"]
403pub enum URSW {
404 #[doc = "Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request"]
405 ANYEVENT,
406 #[doc = "Only counter overflow/underflow generates an update interrupt or DMA request"]
407 COUNTERONLY,
408}
409impl URSW {
410 #[allow(missing_docs)]
411 #[doc(hidden)]
412 #[inline]
413 pub fn _bits(&self) -> bool {
414 match *self {
415 URSW::ANYEVENT => false,
416 URSW::COUNTERONLY => true,
417 }
418 }
419}
420#[doc = r" Proxy"]
421pub struct _URSW<'a> {
422 w: &'a mut W,
423}
424impl<'a> _URSW<'a> {
425 #[doc = r" Writes `variant` to the field"]
426 #[inline]
427 pub fn variant(self, variant: URSW) -> &'a mut W {
428 {
429 self.bit(variant._bits())
430 }
431 }
432 #[doc = "Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request"]
433 #[inline]
434 pub fn any_event(self) -> &'a mut W {
435 self.variant(URSW::ANYEVENT)
436 }
437 #[doc = "Only counter overflow/underflow generates an update interrupt or DMA request"]
438 #[inline]
439 pub fn counter_only(self) -> &'a mut W {
440 self.variant(URSW::COUNTERONLY)
441 }
442 #[doc = r" Sets the field bit"]
443 pub fn set_bit(self) -> &'a mut W {
444 self.bit(true)
445 }
446 #[doc = r" Clears the field bit"]
447 pub fn clear_bit(self) -> &'a mut W {
448 self.bit(false)
449 }
450 #[doc = r" Writes raw bits to the field"]
451 #[inline]
452 pub fn bit(self, value: bool) -> &'a mut W {
453 const MASK: bool = true;
454 const OFFSET: u8 = 2;
455 self.w.bits &= !((MASK as u32) << OFFSET);
456 self.w.bits |= ((value & MASK) as u32) << OFFSET;
457 self.w
458 }
459}
460#[doc = r" Proxy"]
461pub struct _OPMW<'a> {
462 w: &'a mut W,
463}
464impl<'a> _OPMW<'a> {
465 #[doc = r" Sets the field bit"]
466 pub fn set_bit(self) -> &'a mut W {
467 self.bit(true)
468 }
469 #[doc = r" Clears the field bit"]
470 pub fn clear_bit(self) -> &'a mut W {
471 self.bit(false)
472 }
473 #[doc = r" Writes raw bits to the field"]
474 #[inline]
475 pub fn bit(self, value: bool) -> &'a mut W {
476 const MASK: bool = true;
477 const OFFSET: u8 = 3;
478 self.w.bits &= !((MASK as u32) << OFFSET);
479 self.w.bits |= ((value & MASK) as u32) << OFFSET;
480 self.w
481 }
482}
483#[doc = "Values that can be written to the field `ARPE`"]
484pub enum ARPEW {
485 #[doc = "TIMx_APRR register is not buffered"]
486 DISABLED,
487 #[doc = "TIMx_APRR register is buffered"]
488 ENABLED,
489}
490impl ARPEW {
491 #[allow(missing_docs)]
492 #[doc(hidden)]
493 #[inline]
494 pub fn _bits(&self) -> bool {
495 match *self {
496 ARPEW::DISABLED => false,
497 ARPEW::ENABLED => true,
498 }
499 }
500}
501#[doc = r" Proxy"]
502pub struct _ARPEW<'a> {
503 w: &'a mut W,
504}
505impl<'a> _ARPEW<'a> {
506 #[doc = r" Writes `variant` to the field"]
507 #[inline]
508 pub fn variant(self, variant: ARPEW) -> &'a mut W {
509 {
510 self.bit(variant._bits())
511 }
512 }
513 #[doc = "TIMx_APRR register is not buffered"]
514 #[inline]
515 pub fn disabled(self) -> &'a mut W {
516 self.variant(ARPEW::DISABLED)
517 }
518 #[doc = "TIMx_APRR register is buffered"]
519 #[inline]
520 pub fn enabled(self) -> &'a mut W {
521 self.variant(ARPEW::ENABLED)
522 }
523 #[doc = r" Sets the field bit"]
524 pub fn set_bit(self) -> &'a mut W {
525 self.bit(true)
526 }
527 #[doc = r" Clears the field bit"]
528 pub fn clear_bit(self) -> &'a mut W {
529 self.bit(false)
530 }
531 #[doc = r" Writes raw bits to the field"]
532 #[inline]
533 pub fn bit(self, value: bool) -> &'a mut W {
534 const MASK: bool = true;
535 const OFFSET: u8 = 7;
536 self.w.bits &= !((MASK as u32) << OFFSET);
537 self.w.bits |= ((value & MASK) as u32) << OFFSET;
538 self.w
539 }
540}
541#[doc = r" Proxy"]
542pub struct _CKDW<'a> {
543 w: &'a mut W,
544}
545impl<'a> _CKDW<'a> {
546 #[doc = r" Writes raw bits to the field"]
547 #[inline]
548 pub unsafe fn bits(self, value: u8) -> &'a mut W {
549 const MASK: u8 = 3;
550 const OFFSET: u8 = 8;
551 self.w.bits &= !((MASK as u32) << OFFSET);
552 self.w.bits |= ((value & MASK) as u32) << OFFSET;
553 self.w
554 }
555}
556#[doc = r" Proxy"]
557pub struct _UIFREMAPW<'a> {
558 w: &'a mut W,
559}
560impl<'a> _UIFREMAPW<'a> {
561 #[doc = r" Sets the field bit"]
562 pub fn set_bit(self) -> &'a mut W {
563 self.bit(true)
564 }
565 #[doc = r" Clears the field bit"]
566 pub fn clear_bit(self) -> &'a mut W {
567 self.bit(false)
568 }
569 #[doc = r" Writes raw bits to the field"]
570 #[inline]
571 pub fn bit(self, value: bool) -> &'a mut W {
572 const MASK: bool = true;
573 const OFFSET: u8 = 11;
574 self.w.bits &= !((MASK as u32) << OFFSET);
575 self.w.bits |= ((value & MASK) as u32) << OFFSET;
576 self.w
577 }
578}
579impl R {
580 #[doc = r" Value of the register as raw bits"]
581 #[inline]
582 pub fn bits(&self) -> u32 {
583 self.bits
584 }
585 #[doc = "Bit 0 - Counter enable"]
586 #[inline]
587 pub fn cen(&self) -> CENR {
588 CENR::_from({
589 const MASK: bool = true;
590 const OFFSET: u8 = 0;
591 ((self.bits >> OFFSET) & MASK as u32) != 0
592 })
593 }
594 #[doc = "Bit 1 - Update disable"]
595 #[inline]
596 pub fn udis(&self) -> UDISR {
597 UDISR::_from({
598 const MASK: bool = true;
599 const OFFSET: u8 = 1;
600 ((self.bits >> OFFSET) & MASK as u32) != 0
601 })
602 }
603 #[doc = "Bit 2 - Update request source"]
604 #[inline]
605 pub fn urs(&self) -> URSR {
606 URSR::_from({
607 const MASK: bool = true;
608 const OFFSET: u8 = 2;
609 ((self.bits >> OFFSET) & MASK as u32) != 0
610 })
611 }
612 #[doc = "Bit 3 - One-pulse mode"]
613 #[inline]
614 pub fn opm(&self) -> OPMR {
615 let bits = {
616 const MASK: bool = true;
617 const OFFSET: u8 = 3;
618 ((self.bits >> OFFSET) & MASK as u32) != 0
619 };
620 OPMR { bits }
621 }
622 #[doc = "Bit 7 - Auto-reload preload enable"]
623 #[inline]
624 pub fn arpe(&self) -> ARPER {
625 ARPER::_from({
626 const MASK: bool = true;
627 const OFFSET: u8 = 7;
628 ((self.bits >> OFFSET) & MASK as u32) != 0
629 })
630 }
631 #[doc = "Bits 8:9 - Clock division"]
632 #[inline]
633 pub fn ckd(&self) -> CKDR {
634 let bits = {
635 const MASK: u8 = 3;
636 const OFFSET: u8 = 8;
637 ((self.bits >> OFFSET) & MASK as u32) as u8
638 };
639 CKDR { bits }
640 }
641 #[doc = "Bit 11 - UIF status bit remapping"]
642 #[inline]
643 pub fn uifremap(&self) -> UIFREMAPR {
644 let bits = {
645 const MASK: bool = true;
646 const OFFSET: u8 = 11;
647 ((self.bits >> OFFSET) & MASK as u32) != 0
648 };
649 UIFREMAPR { bits }
650 }
651}
652impl W {
653 #[doc = r" Reset value of the register"]
654 #[inline]
655 pub fn reset_value() -> W {
656 W { bits: 0 }
657 }
658 #[doc = r" Writes raw bits to the register"]
659 #[inline]
660 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
661 self.bits = bits;
662 self
663 }
664 #[doc = "Bit 0 - Counter enable"]
665 #[inline]
666 pub fn cen(&mut self) -> _CENW {
667 _CENW { w: self }
668 }
669 #[doc = "Bit 1 - Update disable"]
670 #[inline]
671 pub fn udis(&mut self) -> _UDISW {
672 _UDISW { w: self }
673 }
674 #[doc = "Bit 2 - Update request source"]
675 #[inline]
676 pub fn urs(&mut self) -> _URSW {
677 _URSW { w: self }
678 }
679 #[doc = "Bit 3 - One-pulse mode"]
680 #[inline]
681 pub fn opm(&mut self) -> _OPMW {
682 _OPMW { w: self }
683 }
684 #[doc = "Bit 7 - Auto-reload preload enable"]
685 #[inline]
686 pub fn arpe(&mut self) -> _ARPEW {
687 _ARPEW { w: self }
688 }
689 #[doc = "Bits 8:9 - Clock division"]
690 #[inline]
691 pub fn ckd(&mut self) -> _CKDW {
692 _CKDW { w: self }
693 }
694 #[doc = "Bit 11 - UIF status bit remapping"]
695 #[inline]
696 pub fn uifremap(&mut self) -> _UIFREMAPW {
697 _UIFREMAPW { w: self }
698 }
699}