stm32l4x2_pac/rcc/
ahb1smenr.rs

1#[doc = r" Value read from the register"]
2pub struct R {
3    bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7    bits: u32,
8}
9impl super::AHB1SMENR {
10    #[doc = r" Modifies the contents of the register"]
11    #[inline]
12    pub fn modify<F>(&self, f: F)
13    where
14        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15    {
16        let bits = self.register.get();
17        let r = R { bits: bits };
18        let mut w = W { bits: bits };
19        f(&r, &mut w);
20        self.register.set(w.bits);
21    }
22    #[doc = r" Reads the contents of the register"]
23    #[inline]
24    pub fn read(&self) -> R {
25        R {
26            bits: self.register.get(),
27        }
28    }
29    #[doc = r" Writes to the register"]
30    #[inline]
31    pub fn write<F>(&self, f: F)
32    where
33        F: FnOnce(&mut W) -> &mut W,
34    {
35        let mut w = W::reset_value();
36        f(&mut w);
37        self.register.set(w.bits);
38    }
39    #[doc = r" Writes the reset value to the register"]
40    #[inline]
41    pub fn reset(&self) {
42        self.write(|w| w)
43    }
44}
45#[doc = r" Value of the field"]
46pub struct TSCSMENR {
47    bits: bool,
48}
49impl TSCSMENR {
50    #[doc = r" Value of the field as raw bits"]
51    #[inline]
52    pub fn bit(&self) -> bool {
53        self.bits
54    }
55    #[doc = r" Returns `true` if the bit is clear (0)"]
56    #[inline]
57    pub fn bit_is_clear(&self) -> bool {
58        !self.bit()
59    }
60    #[doc = r" Returns `true` if the bit is set (1)"]
61    #[inline]
62    pub fn bit_is_set(&self) -> bool {
63        self.bit()
64    }
65}
66#[doc = r" Value of the field"]
67pub struct CRCSMENR {
68    bits: bool,
69}
70impl CRCSMENR {
71    #[doc = r" Value of the field as raw bits"]
72    #[inline]
73    pub fn bit(&self) -> bool {
74        self.bits
75    }
76    #[doc = r" Returns `true` if the bit is clear (0)"]
77    #[inline]
78    pub fn bit_is_clear(&self) -> bool {
79        !self.bit()
80    }
81    #[doc = r" Returns `true` if the bit is set (1)"]
82    #[inline]
83    pub fn bit_is_set(&self) -> bool {
84        self.bit()
85    }
86}
87#[doc = r" Value of the field"]
88pub struct SRAM1SMENR {
89    bits: bool,
90}
91impl SRAM1SMENR {
92    #[doc = r" Value of the field as raw bits"]
93    #[inline]
94    pub fn bit(&self) -> bool {
95        self.bits
96    }
97    #[doc = r" Returns `true` if the bit is clear (0)"]
98    #[inline]
99    pub fn bit_is_clear(&self) -> bool {
100        !self.bit()
101    }
102    #[doc = r" Returns `true` if the bit is set (1)"]
103    #[inline]
104    pub fn bit_is_set(&self) -> bool {
105        self.bit()
106    }
107}
108#[doc = r" Value of the field"]
109pub struct FLASHSMENR {
110    bits: bool,
111}
112impl FLASHSMENR {
113    #[doc = r" Value of the field as raw bits"]
114    #[inline]
115    pub fn bit(&self) -> bool {
116        self.bits
117    }
118    #[doc = r" Returns `true` if the bit is clear (0)"]
119    #[inline]
120    pub fn bit_is_clear(&self) -> bool {
121        !self.bit()
122    }
123    #[doc = r" Returns `true` if the bit is set (1)"]
124    #[inline]
125    pub fn bit_is_set(&self) -> bool {
126        self.bit()
127    }
128}
129#[doc = r" Value of the field"]
130pub struct DMA2SMENR {
131    bits: bool,
132}
133impl DMA2SMENR {
134    #[doc = r" Value of the field as raw bits"]
135    #[inline]
136    pub fn bit(&self) -> bool {
137        self.bits
138    }
139    #[doc = r" Returns `true` if the bit is clear (0)"]
140    #[inline]
141    pub fn bit_is_clear(&self) -> bool {
142        !self.bit()
143    }
144    #[doc = r" Returns `true` if the bit is set (1)"]
145    #[inline]
146    pub fn bit_is_set(&self) -> bool {
147        self.bit()
148    }
149}
150#[doc = r" Value of the field"]
151pub struct DMA1SMENR {
152    bits: bool,
153}
154impl DMA1SMENR {
155    #[doc = r" Value of the field as raw bits"]
156    #[inline]
157    pub fn bit(&self) -> bool {
158        self.bits
159    }
160    #[doc = r" Returns `true` if the bit is clear (0)"]
161    #[inline]
162    pub fn bit_is_clear(&self) -> bool {
163        !self.bit()
164    }
165    #[doc = r" Returns `true` if the bit is set (1)"]
166    #[inline]
167    pub fn bit_is_set(&self) -> bool {
168        self.bit()
169    }
170}
171#[doc = r" Proxy"]
172pub struct _TSCSMENW<'a> {
173    w: &'a mut W,
174}
175impl<'a> _TSCSMENW<'a> {
176    #[doc = r" Sets the field bit"]
177    pub fn set_bit(self) -> &'a mut W {
178        self.bit(true)
179    }
180    #[doc = r" Clears the field bit"]
181    pub fn clear_bit(self) -> &'a mut W {
182        self.bit(false)
183    }
184    #[doc = r" Writes raw bits to the field"]
185    #[inline]
186    pub fn bit(self, value: bool) -> &'a mut W {
187        const MASK: bool = true;
188        const OFFSET: u8 = 16;
189        self.w.bits &= !((MASK as u32) << OFFSET);
190        self.w.bits |= ((value & MASK) as u32) << OFFSET;
191        self.w
192    }
193}
194#[doc = r" Proxy"]
195pub struct _CRCSMENW<'a> {
196    w: &'a mut W,
197}
198impl<'a> _CRCSMENW<'a> {
199    #[doc = r" Sets the field bit"]
200    pub fn set_bit(self) -> &'a mut W {
201        self.bit(true)
202    }
203    #[doc = r" Clears the field bit"]
204    pub fn clear_bit(self) -> &'a mut W {
205        self.bit(false)
206    }
207    #[doc = r" Writes raw bits to the field"]
208    #[inline]
209    pub fn bit(self, value: bool) -> &'a mut W {
210        const MASK: bool = true;
211        const OFFSET: u8 = 12;
212        self.w.bits &= !((MASK as u32) << OFFSET);
213        self.w.bits |= ((value & MASK) as u32) << OFFSET;
214        self.w
215    }
216}
217#[doc = r" Proxy"]
218pub struct _SRAM1SMENW<'a> {
219    w: &'a mut W,
220}
221impl<'a> _SRAM1SMENW<'a> {
222    #[doc = r" Sets the field bit"]
223    pub fn set_bit(self) -> &'a mut W {
224        self.bit(true)
225    }
226    #[doc = r" Clears the field bit"]
227    pub fn clear_bit(self) -> &'a mut W {
228        self.bit(false)
229    }
230    #[doc = r" Writes raw bits to the field"]
231    #[inline]
232    pub fn bit(self, value: bool) -> &'a mut W {
233        const MASK: bool = true;
234        const OFFSET: u8 = 9;
235        self.w.bits &= !((MASK as u32) << OFFSET);
236        self.w.bits |= ((value & MASK) as u32) << OFFSET;
237        self.w
238    }
239}
240#[doc = r" Proxy"]
241pub struct _FLASHSMENW<'a> {
242    w: &'a mut W,
243}
244impl<'a> _FLASHSMENW<'a> {
245    #[doc = r" Sets the field bit"]
246    pub fn set_bit(self) -> &'a mut W {
247        self.bit(true)
248    }
249    #[doc = r" Clears the field bit"]
250    pub fn clear_bit(self) -> &'a mut W {
251        self.bit(false)
252    }
253    #[doc = r" Writes raw bits to the field"]
254    #[inline]
255    pub fn bit(self, value: bool) -> &'a mut W {
256        const MASK: bool = true;
257        const OFFSET: u8 = 8;
258        self.w.bits &= !((MASK as u32) << OFFSET);
259        self.w.bits |= ((value & MASK) as u32) << OFFSET;
260        self.w
261    }
262}
263#[doc = r" Proxy"]
264pub struct _DMA2SMENW<'a> {
265    w: &'a mut W,
266}
267impl<'a> _DMA2SMENW<'a> {
268    #[doc = r" Sets the field bit"]
269    pub fn set_bit(self) -> &'a mut W {
270        self.bit(true)
271    }
272    #[doc = r" Clears the field bit"]
273    pub fn clear_bit(self) -> &'a mut W {
274        self.bit(false)
275    }
276    #[doc = r" Writes raw bits to the field"]
277    #[inline]
278    pub fn bit(self, value: bool) -> &'a mut W {
279        const MASK: bool = true;
280        const OFFSET: u8 = 1;
281        self.w.bits &= !((MASK as u32) << OFFSET);
282        self.w.bits |= ((value & MASK) as u32) << OFFSET;
283        self.w
284    }
285}
286#[doc = r" Proxy"]
287pub struct _DMA1SMENW<'a> {
288    w: &'a mut W,
289}
290impl<'a> _DMA1SMENW<'a> {
291    #[doc = r" Sets the field bit"]
292    pub fn set_bit(self) -> &'a mut W {
293        self.bit(true)
294    }
295    #[doc = r" Clears the field bit"]
296    pub fn clear_bit(self) -> &'a mut W {
297        self.bit(false)
298    }
299    #[doc = r" Writes raw bits to the field"]
300    #[inline]
301    pub fn bit(self, value: bool) -> &'a mut W {
302        const MASK: bool = true;
303        const OFFSET: u8 = 0;
304        self.w.bits &= !((MASK as u32) << OFFSET);
305        self.w.bits |= ((value & MASK) as u32) << OFFSET;
306        self.w
307    }
308}
309impl R {
310    #[doc = r" Value of the register as raw bits"]
311    #[inline]
312    pub fn bits(&self) -> u32 {
313        self.bits
314    }
315    #[doc = "Bit 16 - Touch Sensing Controller clocks enable during Sleep and Stop modes"]
316    #[inline]
317    pub fn tscsmen(&self) -> TSCSMENR {
318        let bits = {
319            const MASK: bool = true;
320            const OFFSET: u8 = 16;
321            ((self.bits >> OFFSET) & MASK as u32) != 0
322        };
323        TSCSMENR { bits }
324    }
325    #[doc = "Bit 12 - CRCSMEN"]
326    #[inline]
327    pub fn crcsmen(&self) -> CRCSMENR {
328        let bits = {
329            const MASK: bool = true;
330            const OFFSET: u8 = 12;
331            ((self.bits >> OFFSET) & MASK as u32) != 0
332        };
333        CRCSMENR { bits }
334    }
335    #[doc = "Bit 9 - SRAM1 interface clocks enable during Sleep and Stop modes"]
336    #[inline]
337    pub fn sram1smen(&self) -> SRAM1SMENR {
338        let bits = {
339            const MASK: bool = true;
340            const OFFSET: u8 = 9;
341            ((self.bits >> OFFSET) & MASK as u32) != 0
342        };
343        SRAM1SMENR { bits }
344    }
345    #[doc = "Bit 8 - Flash memory interface clocks enable during Sleep and Stop modes"]
346    #[inline]
347    pub fn flashsmen(&self) -> FLASHSMENR {
348        let bits = {
349            const MASK: bool = true;
350            const OFFSET: u8 = 8;
351            ((self.bits >> OFFSET) & MASK as u32) != 0
352        };
353        FLASHSMENR { bits }
354    }
355    #[doc = "Bit 1 - DMA2 clocks enable during Sleep and Stop modes"]
356    #[inline]
357    pub fn dma2smen(&self) -> DMA2SMENR {
358        let bits = {
359            const MASK: bool = true;
360            const OFFSET: u8 = 1;
361            ((self.bits >> OFFSET) & MASK as u32) != 0
362        };
363        DMA2SMENR { bits }
364    }
365    #[doc = "Bit 0 - DMA1 clocks enable during Sleep and Stop modes"]
366    #[inline]
367    pub fn dma1smen(&self) -> DMA1SMENR {
368        let bits = {
369            const MASK: bool = true;
370            const OFFSET: u8 = 0;
371            ((self.bits >> OFFSET) & MASK as u32) != 0
372        };
373        DMA1SMENR { bits }
374    }
375}
376impl W {
377    #[doc = r" Reset value of the register"]
378    #[inline]
379    pub fn reset_value() -> W {
380        W { bits: 70403 }
381    }
382    #[doc = r" Writes raw bits to the register"]
383    #[inline]
384    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
385        self.bits = bits;
386        self
387    }
388    #[doc = "Bit 16 - Touch Sensing Controller clocks enable during Sleep and Stop modes"]
389    #[inline]
390    pub fn tscsmen(&mut self) -> _TSCSMENW {
391        _TSCSMENW { w: self }
392    }
393    #[doc = "Bit 12 - CRCSMEN"]
394    #[inline]
395    pub fn crcsmen(&mut self) -> _CRCSMENW {
396        _CRCSMENW { w: self }
397    }
398    #[doc = "Bit 9 - SRAM1 interface clocks enable during Sleep and Stop modes"]
399    #[inline]
400    pub fn sram1smen(&mut self) -> _SRAM1SMENW {
401        _SRAM1SMENW { w: self }
402    }
403    #[doc = "Bit 8 - Flash memory interface clocks enable during Sleep and Stop modes"]
404    #[inline]
405    pub fn flashsmen(&mut self) -> _FLASHSMENW {
406        _FLASHSMENW { w: self }
407    }
408    #[doc = "Bit 1 - DMA2 clocks enable during Sleep and Stop modes"]
409    #[inline]
410    pub fn dma2smen(&mut self) -> _DMA2SMENW {
411        _DMA2SMENW { w: self }
412    }
413    #[doc = "Bit 0 - DMA1 clocks enable during Sleep and Stop modes"]
414    #[inline]
415    pub fn dma1smen(&mut self) -> _DMA1SMENW {
416        _DMA1SMENW { w: self }
417    }
418}
stm32l4x2_pac/rcc/ahb1smenr.rs

stm32l4x2_pac/rcc/
ahb1smenr.rs
