1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::CR3 {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = "Possible values of the field `WUFIE`"]
46#[derive(Clone, Copy, Debug, PartialEq)]
47pub enum WUFIER {
48 #[doc = "Interrupt is inhibited"]
49 DISABLED,
50 #[doc = "An USART interrupt is generated whenever WUF=1 in the ISR register"]
51 ENABLED,
52}
53impl WUFIER {
54 #[doc = r" Returns `true` if the bit is clear (0)"]
55 #[inline]
56 pub fn bit_is_clear(&self) -> bool {
57 !self.bit()
58 }
59 #[doc = r" Returns `true` if the bit is set (1)"]
60 #[inline]
61 pub fn bit_is_set(&self) -> bool {
62 self.bit()
63 }
64 #[doc = r" Value of the field as raw bits"]
65 #[inline]
66 pub fn bit(&self) -> bool {
67 match *self {
68 WUFIER::DISABLED => false,
69 WUFIER::ENABLED => true,
70 }
71 }
72 #[allow(missing_docs)]
73 #[doc(hidden)]
74 #[inline]
75 pub fn _from(value: bool) -> WUFIER {
76 match value {
77 false => WUFIER::DISABLED,
78 true => WUFIER::ENABLED,
79 }
80 }
81 #[doc = "Checks if the value of the field is `DISABLED`"]
82 #[inline]
83 pub fn is_disabled(&self) -> bool {
84 *self == WUFIER::DISABLED
85 }
86 #[doc = "Checks if the value of the field is `ENABLED`"]
87 #[inline]
88 pub fn is_enabled(&self) -> bool {
89 *self == WUFIER::ENABLED
90 }
91}
92#[doc = "Possible values of the field `WUS`"]
93#[derive(Clone, Copy, Debug, PartialEq)]
94pub enum WUSR {
95 #[doc = "WUF active on address match"]
96 ADDRESS,
97 #[doc = "WuF active on Start bit detection"]
98 START,
99 #[doc = "WUF active on RXNE"]
100 RXNE,
101 #[doc = r" Reserved"]
102 _Reserved(u8),
103}
104impl WUSR {
105 #[doc = r" Value of the field as raw bits"]
106 #[inline]
107 pub fn bits(&self) -> u8 {
108 match *self {
109 WUSR::ADDRESS => 0,
110 WUSR::START => 2,
111 WUSR::RXNE => 3,
112 WUSR::_Reserved(bits) => bits,
113 }
114 }
115 #[allow(missing_docs)]
116 #[doc(hidden)]
117 #[inline]
118 pub fn _from(value: u8) -> WUSR {
119 match value {
120 0 => WUSR::ADDRESS,
121 2 => WUSR::START,
122 3 => WUSR::RXNE,
123 i => WUSR::_Reserved(i),
124 }
125 }
126 #[doc = "Checks if the value of the field is `ADDRESS`"]
127 #[inline]
128 pub fn is_address(&self) -> bool {
129 *self == WUSR::ADDRESS
130 }
131 #[doc = "Checks if the value of the field is `START`"]
132 #[inline]
133 pub fn is_start(&self) -> bool {
134 *self == WUSR::START
135 }
136 #[doc = "Checks if the value of the field is `RXNE`"]
137 #[inline]
138 pub fn is_rxne(&self) -> bool {
139 *self == WUSR::RXNE
140 }
141}
142#[doc = "Possible values of the field `DEP`"]
143#[derive(Clone, Copy, Debug, PartialEq)]
144pub enum DEPR {
145 #[doc = "DE signal is active high"]
146 HIGH,
147 #[doc = "DE signal is active low"]
148 LOW,
149}
150impl DEPR {
151 #[doc = r" Returns `true` if the bit is clear (0)"]
152 #[inline]
153 pub fn bit_is_clear(&self) -> bool {
154 !self.bit()
155 }
156 #[doc = r" Returns `true` if the bit is set (1)"]
157 #[inline]
158 pub fn bit_is_set(&self) -> bool {
159 self.bit()
160 }
161 #[doc = r" Value of the field as raw bits"]
162 #[inline]
163 pub fn bit(&self) -> bool {
164 match *self {
165 DEPR::HIGH => false,
166 DEPR::LOW => true,
167 }
168 }
169 #[allow(missing_docs)]
170 #[doc(hidden)]
171 #[inline]
172 pub fn _from(value: bool) -> DEPR {
173 match value {
174 false => DEPR::HIGH,
175 true => DEPR::LOW,
176 }
177 }
178 #[doc = "Checks if the value of the field is `HIGH`"]
179 #[inline]
180 pub fn is_high(&self) -> bool {
181 *self == DEPR::HIGH
182 }
183 #[doc = "Checks if the value of the field is `LOW`"]
184 #[inline]
185 pub fn is_low(&self) -> bool {
186 *self == DEPR::LOW
187 }
188}
189#[doc = "Possible values of the field `DEM`"]
190#[derive(Clone, Copy, Debug, PartialEq)]
191pub enum DEMR {
192 #[doc = "DE function is disabled"]
193 DISABLED,
194 #[doc = "The DE signal is output on the RTS pin"]
195 ENABLED,
196}
197impl DEMR {
198 #[doc = r" Returns `true` if the bit is clear (0)"]
199 #[inline]
200 pub fn bit_is_clear(&self) -> bool {
201 !self.bit()
202 }
203 #[doc = r" Returns `true` if the bit is set (1)"]
204 #[inline]
205 pub fn bit_is_set(&self) -> bool {
206 self.bit()
207 }
208 #[doc = r" Value of the field as raw bits"]
209 #[inline]
210 pub fn bit(&self) -> bool {
211 match *self {
212 DEMR::DISABLED => false,
213 DEMR::ENABLED => true,
214 }
215 }
216 #[allow(missing_docs)]
217 #[doc(hidden)]
218 #[inline]
219 pub fn _from(value: bool) -> DEMR {
220 match value {
221 false => DEMR::DISABLED,
222 true => DEMR::ENABLED,
223 }
224 }
225 #[doc = "Checks if the value of the field is `DISABLED`"]
226 #[inline]
227 pub fn is_disabled(&self) -> bool {
228 *self == DEMR::DISABLED
229 }
230 #[doc = "Checks if the value of the field is `ENABLED`"]
231 #[inline]
232 pub fn is_enabled(&self) -> bool {
233 *self == DEMR::ENABLED
234 }
235}
236#[doc = "Possible values of the field `DDRE`"]
237#[derive(Clone, Copy, Debug, PartialEq)]
238pub enum DDRER {
239 #[doc = "DMA is not disabled in case of reception error"]
240 NOTDISABLED,
241 #[doc = "DMA is disabled following a reception error"]
242 DISABLED,
243}
244impl DDRER {
245 #[doc = r" Returns `true` if the bit is clear (0)"]
246 #[inline]
247 pub fn bit_is_clear(&self) -> bool {
248 !self.bit()
249 }
250 #[doc = r" Returns `true` if the bit is set (1)"]
251 #[inline]
252 pub fn bit_is_set(&self) -> bool {
253 self.bit()
254 }
255 #[doc = r" Value of the field as raw bits"]
256 #[inline]
257 pub fn bit(&self) -> bool {
258 match *self {
259 DDRER::NOTDISABLED => false,
260 DDRER::DISABLED => true,
261 }
262 }
263 #[allow(missing_docs)]
264 #[doc(hidden)]
265 #[inline]
266 pub fn _from(value: bool) -> DDRER {
267 match value {
268 false => DDRER::NOTDISABLED,
269 true => DDRER::DISABLED,
270 }
271 }
272 #[doc = "Checks if the value of the field is `NOTDISABLED`"]
273 #[inline]
274 pub fn is_not_disabled(&self) -> bool {
275 *self == DDRER::NOTDISABLED
276 }
277 #[doc = "Checks if the value of the field is `DISABLED`"]
278 #[inline]
279 pub fn is_disabled(&self) -> bool {
280 *self == DDRER::DISABLED
281 }
282}
283#[doc = "Possible values of the field `OVRDIS`"]
284#[derive(Clone, Copy, Debug, PartialEq)]
285pub enum OVRDISR {
286 #[doc = "Overrun Error Flag, ORE, is set when received data is not read before receiving new data"]
287 ENABLED,
288 #[doc = "Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register"]
289 DISABLED,
290}
291impl OVRDISR {
292 #[doc = r" Returns `true` if the bit is clear (0)"]
293 #[inline]
294 pub fn bit_is_clear(&self) -> bool {
295 !self.bit()
296 }
297 #[doc = r" Returns `true` if the bit is set (1)"]
298 #[inline]
299 pub fn bit_is_set(&self) -> bool {
300 self.bit()
301 }
302 #[doc = r" Value of the field as raw bits"]
303 #[inline]
304 pub fn bit(&self) -> bool {
305 match *self {
306 OVRDISR::ENABLED => false,
307 OVRDISR::DISABLED => true,
308 }
309 }
310 #[allow(missing_docs)]
311 #[doc(hidden)]
312 #[inline]
313 pub fn _from(value: bool) -> OVRDISR {
314 match value {
315 false => OVRDISR::ENABLED,
316 true => OVRDISR::DISABLED,
317 }
318 }
319 #[doc = "Checks if the value of the field is `ENABLED`"]
320 #[inline]
321 pub fn is_enabled(&self) -> bool {
322 *self == OVRDISR::ENABLED
323 }
324 #[doc = "Checks if the value of the field is `DISABLED`"]
325 #[inline]
326 pub fn is_disabled(&self) -> bool {
327 *self == OVRDISR::DISABLED
328 }
329}
330#[doc = "Possible values of the field `CTSIE`"]
331#[derive(Clone, Copy, Debug, PartialEq)]
332pub enum CTSIER {
333 #[doc = "Interrupt is inhibited"]
334 DISABLED,
335 #[doc = "An interrupt is generated whenever CTSIF=1 in the ISR register"]
336 ENABLED,
337}
338impl CTSIER {
339 #[doc = r" Returns `true` if the bit is clear (0)"]
340 #[inline]
341 pub fn bit_is_clear(&self) -> bool {
342 !self.bit()
343 }
344 #[doc = r" Returns `true` if the bit is set (1)"]
345 #[inline]
346 pub fn bit_is_set(&self) -> bool {
347 self.bit()
348 }
349 #[doc = r" Value of the field as raw bits"]
350 #[inline]
351 pub fn bit(&self) -> bool {
352 match *self {
353 CTSIER::DISABLED => false,
354 CTSIER::ENABLED => true,
355 }
356 }
357 #[allow(missing_docs)]
358 #[doc(hidden)]
359 #[inline]
360 pub fn _from(value: bool) -> CTSIER {
361 match value {
362 false => CTSIER::DISABLED,
363 true => CTSIER::ENABLED,
364 }
365 }
366 #[doc = "Checks if the value of the field is `DISABLED`"]
367 #[inline]
368 pub fn is_disabled(&self) -> bool {
369 *self == CTSIER::DISABLED
370 }
371 #[doc = "Checks if the value of the field is `ENABLED`"]
372 #[inline]
373 pub fn is_enabled(&self) -> bool {
374 *self == CTSIER::ENABLED
375 }
376}
377#[doc = "Possible values of the field `CTSE`"]
378#[derive(Clone, Copy, Debug, PartialEq)]
379pub enum CTSER {
380 #[doc = "CTS hardware flow control disabled"]
381 DISABLED,
382 #[doc = "CTS mode enabled, data is only transmitted when the CTS input is asserted"]
383 ENABLED,
384}
385impl CTSER {
386 #[doc = r" Returns `true` if the bit is clear (0)"]
387 #[inline]
388 pub fn bit_is_clear(&self) -> bool {
389 !self.bit()
390 }
391 #[doc = r" Returns `true` if the bit is set (1)"]
392 #[inline]
393 pub fn bit_is_set(&self) -> bool {
394 self.bit()
395 }
396 #[doc = r" Value of the field as raw bits"]
397 #[inline]
398 pub fn bit(&self) -> bool {
399 match *self {
400 CTSER::DISABLED => false,
401 CTSER::ENABLED => true,
402 }
403 }
404 #[allow(missing_docs)]
405 #[doc(hidden)]
406 #[inline]
407 pub fn _from(value: bool) -> CTSER {
408 match value {
409 false => CTSER::DISABLED,
410 true => CTSER::ENABLED,
411 }
412 }
413 #[doc = "Checks if the value of the field is `DISABLED`"]
414 #[inline]
415 pub fn is_disabled(&self) -> bool {
416 *self == CTSER::DISABLED
417 }
418 #[doc = "Checks if the value of the field is `ENABLED`"]
419 #[inline]
420 pub fn is_enabled(&self) -> bool {
421 *self == CTSER::ENABLED
422 }
423}
424#[doc = "Possible values of the field `RTSE`"]
425#[derive(Clone, Copy, Debug, PartialEq)]
426pub enum RTSER {
427 #[doc = "RTS hardware flow control disabled"]
428 DISABLED,
429 #[doc = "RTS output enabled, data is only requested when there is space in the receive buffer"]
430 ENABLED,
431}
432impl RTSER {
433 #[doc = r" Returns `true` if the bit is clear (0)"]
434 #[inline]
435 pub fn bit_is_clear(&self) -> bool {
436 !self.bit()
437 }
438 #[doc = r" Returns `true` if the bit is set (1)"]
439 #[inline]
440 pub fn bit_is_set(&self) -> bool {
441 self.bit()
442 }
443 #[doc = r" Value of the field as raw bits"]
444 #[inline]
445 pub fn bit(&self) -> bool {
446 match *self {
447 RTSER::DISABLED => false,
448 RTSER::ENABLED => true,
449 }
450 }
451 #[allow(missing_docs)]
452 #[doc(hidden)]
453 #[inline]
454 pub fn _from(value: bool) -> RTSER {
455 match value {
456 false => RTSER::DISABLED,
457 true => RTSER::ENABLED,
458 }
459 }
460 #[doc = "Checks if the value of the field is `DISABLED`"]
461 #[inline]
462 pub fn is_disabled(&self) -> bool {
463 *self == RTSER::DISABLED
464 }
465 #[doc = "Checks if the value of the field is `ENABLED`"]
466 #[inline]
467 pub fn is_enabled(&self) -> bool {
468 *self == RTSER::ENABLED
469 }
470}
471#[doc = "Possible values of the field `DMAT`"]
472#[derive(Clone, Copy, Debug, PartialEq)]
473pub enum DMATR {
474 #[doc = "DMA mode is disabled for transmission"]
475 DISABLED,
476 #[doc = "DMA mode is enabled for transmission"]
477 ENABLED,
478}
479impl DMATR {
480 #[doc = r" Returns `true` if the bit is clear (0)"]
481 #[inline]
482 pub fn bit_is_clear(&self) -> bool {
483 !self.bit()
484 }
485 #[doc = r" Returns `true` if the bit is set (1)"]
486 #[inline]
487 pub fn bit_is_set(&self) -> bool {
488 self.bit()
489 }
490 #[doc = r" Value of the field as raw bits"]
491 #[inline]
492 pub fn bit(&self) -> bool {
493 match *self {
494 DMATR::DISABLED => false,
495 DMATR::ENABLED => true,
496 }
497 }
498 #[allow(missing_docs)]
499 #[doc(hidden)]
500 #[inline]
501 pub fn _from(value: bool) -> DMATR {
502 match value {
503 false => DMATR::DISABLED,
504 true => DMATR::ENABLED,
505 }
506 }
507 #[doc = "Checks if the value of the field is `DISABLED`"]
508 #[inline]
509 pub fn is_disabled(&self) -> bool {
510 *self == DMATR::DISABLED
511 }
512 #[doc = "Checks if the value of the field is `ENABLED`"]
513 #[inline]
514 pub fn is_enabled(&self) -> bool {
515 *self == DMATR::ENABLED
516 }
517}
518#[doc = "Possible values of the field `DMAR`"]
519#[derive(Clone, Copy, Debug, PartialEq)]
520pub enum DMARR {
521 #[doc = "DMA mode is disabled for reception"]
522 DISABLED,
523 #[doc = "DMA mode is enabled for reception"]
524 ENABLED,
525}
526impl DMARR {
527 #[doc = r" Returns `true` if the bit is clear (0)"]
528 #[inline]
529 pub fn bit_is_clear(&self) -> bool {
530 !self.bit()
531 }
532 #[doc = r" Returns `true` if the bit is set (1)"]
533 #[inline]
534 pub fn bit_is_set(&self) -> bool {
535 self.bit()
536 }
537 #[doc = r" Value of the field as raw bits"]
538 #[inline]
539 pub fn bit(&self) -> bool {
540 match *self {
541 DMARR::DISABLED => false,
542 DMARR::ENABLED => true,
543 }
544 }
545 #[allow(missing_docs)]
546 #[doc(hidden)]
547 #[inline]
548 pub fn _from(value: bool) -> DMARR {
549 match value {
550 false => DMARR::DISABLED,
551 true => DMARR::ENABLED,
552 }
553 }
554 #[doc = "Checks if the value of the field is `DISABLED`"]
555 #[inline]
556 pub fn is_disabled(&self) -> bool {
557 *self == DMARR::DISABLED
558 }
559 #[doc = "Checks if the value of the field is `ENABLED`"]
560 #[inline]
561 pub fn is_enabled(&self) -> bool {
562 *self == DMARR::ENABLED
563 }
564}
565#[doc = "Possible values of the field `HDSEL`"]
566#[derive(Clone, Copy, Debug, PartialEq)]
567pub enum HDSELR {
568 #[doc = "Half duplex mode is not selected"]
569 NOTSELECTED,
570 #[doc = "Half duplex mode is selected"]
571 SELECTED,
572}
573impl HDSELR {
574 #[doc = r" Returns `true` if the bit is clear (0)"]
575 #[inline]
576 pub fn bit_is_clear(&self) -> bool {
577 !self.bit()
578 }
579 #[doc = r" Returns `true` if the bit is set (1)"]
580 #[inline]
581 pub fn bit_is_set(&self) -> bool {
582 self.bit()
583 }
584 #[doc = r" Value of the field as raw bits"]
585 #[inline]
586 pub fn bit(&self) -> bool {
587 match *self {
588 HDSELR::NOTSELECTED => false,
589 HDSELR::SELECTED => true,
590 }
591 }
592 #[allow(missing_docs)]
593 #[doc(hidden)]
594 #[inline]
595 pub fn _from(value: bool) -> HDSELR {
596 match value {
597 false => HDSELR::NOTSELECTED,
598 true => HDSELR::SELECTED,
599 }
600 }
601 #[doc = "Checks if the value of the field is `NOTSELECTED`"]
602 #[inline]
603 pub fn is_not_selected(&self) -> bool {
604 *self == HDSELR::NOTSELECTED
605 }
606 #[doc = "Checks if the value of the field is `SELECTED`"]
607 #[inline]
608 pub fn is_selected(&self) -> bool {
609 *self == HDSELR::SELECTED
610 }
611}
612#[doc = "Possible values of the field `EIE`"]
613#[derive(Clone, Copy, Debug, PartialEq)]
614pub enum EIER {
615 #[doc = "Interrupt is inhibited"]
616 DISABLED,
617 #[doc = "An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register"]
618 ENABLED,
619}
620impl EIER {
621 #[doc = r" Returns `true` if the bit is clear (0)"]
622 #[inline]
623 pub fn bit_is_clear(&self) -> bool {
624 !self.bit()
625 }
626 #[doc = r" Returns `true` if the bit is set (1)"]
627 #[inline]
628 pub fn bit_is_set(&self) -> bool {
629 self.bit()
630 }
631 #[doc = r" Value of the field as raw bits"]
632 #[inline]
633 pub fn bit(&self) -> bool {
634 match *self {
635 EIER::DISABLED => false,
636 EIER::ENABLED => true,
637 }
638 }
639 #[allow(missing_docs)]
640 #[doc(hidden)]
641 #[inline]
642 pub fn _from(value: bool) -> EIER {
643 match value {
644 false => EIER::DISABLED,
645 true => EIER::ENABLED,
646 }
647 }
648 #[doc = "Checks if the value of the field is `DISABLED`"]
649 #[inline]
650 pub fn is_disabled(&self) -> bool {
651 *self == EIER::DISABLED
652 }
653 #[doc = "Checks if the value of the field is `ENABLED`"]
654 #[inline]
655 pub fn is_enabled(&self) -> bool {
656 *self == EIER::ENABLED
657 }
658}
659#[doc = "Values that can be written to the field `WUFIE`"]
660pub enum WUFIEW {
661 #[doc = "Interrupt is inhibited"]
662 DISABLED,
663 #[doc = "An USART interrupt is generated whenever WUF=1 in the ISR register"]
664 ENABLED,
665}
666impl WUFIEW {
667 #[allow(missing_docs)]
668 #[doc(hidden)]
669 #[inline]
670 pub fn _bits(&self) -> bool {
671 match *self {
672 WUFIEW::DISABLED => false,
673 WUFIEW::ENABLED => true,
674 }
675 }
676}
677#[doc = r" Proxy"]
678pub struct _WUFIEW<'a> {
679 w: &'a mut W,
680}
681impl<'a> _WUFIEW<'a> {
682 #[doc = r" Writes `variant` to the field"]
683 #[inline]
684 pub fn variant(self, variant: WUFIEW) -> &'a mut W {
685 {
686 self.bit(variant._bits())
687 }
688 }
689 #[doc = "Interrupt is inhibited"]
690 #[inline]
691 pub fn disabled(self) -> &'a mut W {
692 self.variant(WUFIEW::DISABLED)
693 }
694 #[doc = "An USART interrupt is generated whenever WUF=1 in the ISR register"]
695 #[inline]
696 pub fn enabled(self) -> &'a mut W {
697 self.variant(WUFIEW::ENABLED)
698 }
699 #[doc = r" Sets the field bit"]
700 pub fn set_bit(self) -> &'a mut W {
701 self.bit(true)
702 }
703 #[doc = r" Clears the field bit"]
704 pub fn clear_bit(self) -> &'a mut W {
705 self.bit(false)
706 }
707 #[doc = r" Writes raw bits to the field"]
708 #[inline]
709 pub fn bit(self, value: bool) -> &'a mut W {
710 const MASK: bool = true;
711 const OFFSET: u8 = 22;
712 self.w.bits &= !((MASK as u32) << OFFSET);
713 self.w.bits |= ((value & MASK) as u32) << OFFSET;
714 self.w
715 }
716}
717#[doc = "Values that can be written to the field `WUS`"]
718pub enum WUSW {
719 #[doc = "WUF active on address match"]
720 ADDRESS,
721 #[doc = "WuF active on Start bit detection"]
722 START,
723 #[doc = "WUF active on RXNE"]
724 RXNE,
725}
726impl WUSW {
727 #[allow(missing_docs)]
728 #[doc(hidden)]
729 #[inline]
730 pub fn _bits(&self) -> u8 {
731 match *self {
732 WUSW::ADDRESS => 0,
733 WUSW::START => 2,
734 WUSW::RXNE => 3,
735 }
736 }
737}
738#[doc = r" Proxy"]
739pub struct _WUSW<'a> {
740 w: &'a mut W,
741}
742impl<'a> _WUSW<'a> {
743 #[doc = r" Writes `variant` to the field"]
744 #[inline]
745 pub fn variant(self, variant: WUSW) -> &'a mut W {
746 unsafe { self.bits(variant._bits()) }
747 }
748 #[doc = "WUF active on address match"]
749 #[inline]
750 pub fn address(self) -> &'a mut W {
751 self.variant(WUSW::ADDRESS)
752 }
753 #[doc = "WuF active on Start bit detection"]
754 #[inline]
755 pub fn start(self) -> &'a mut W {
756 self.variant(WUSW::START)
757 }
758 #[doc = "WUF active on RXNE"]
759 #[inline]
760 pub fn rxne(self) -> &'a mut W {
761 self.variant(WUSW::RXNE)
762 }
763 #[doc = r" Writes raw bits to the field"]
764 #[inline]
765 pub unsafe fn bits(self, value: u8) -> &'a mut W {
766 const MASK: u8 = 3;
767 const OFFSET: u8 = 20;
768 self.w.bits &= !((MASK as u32) << OFFSET);
769 self.w.bits |= ((value & MASK) as u32) << OFFSET;
770 self.w
771 }
772}
773#[doc = "Values that can be written to the field `DEP`"]
774pub enum DEPW {
775 #[doc = "DE signal is active high"]
776 HIGH,
777 #[doc = "DE signal is active low"]
778 LOW,
779}
780impl DEPW {
781 #[allow(missing_docs)]
782 #[doc(hidden)]
783 #[inline]
784 pub fn _bits(&self) -> bool {
785 match *self {
786 DEPW::HIGH => false,
787 DEPW::LOW => true,
788 }
789 }
790}
791#[doc = r" Proxy"]
792pub struct _DEPW<'a> {
793 w: &'a mut W,
794}
795impl<'a> _DEPW<'a> {
796 #[doc = r" Writes `variant` to the field"]
797 #[inline]
798 pub fn variant(self, variant: DEPW) -> &'a mut W {
799 {
800 self.bit(variant._bits())
801 }
802 }
803 #[doc = "DE signal is active high"]
804 #[inline]
805 pub fn high(self) -> &'a mut W {
806 self.variant(DEPW::HIGH)
807 }
808 #[doc = "DE signal is active low"]
809 #[inline]
810 pub fn low(self) -> &'a mut W {
811 self.variant(DEPW::LOW)
812 }
813 #[doc = r" Sets the field bit"]
814 pub fn set_bit(self) -> &'a mut W {
815 self.bit(true)
816 }
817 #[doc = r" Clears the field bit"]
818 pub fn clear_bit(self) -> &'a mut W {
819 self.bit(false)
820 }
821 #[doc = r" Writes raw bits to the field"]
822 #[inline]
823 pub fn bit(self, value: bool) -> &'a mut W {
824 const MASK: bool = true;
825 const OFFSET: u8 = 15;
826 self.w.bits &= !((MASK as u32) << OFFSET);
827 self.w.bits |= ((value & MASK) as u32) << OFFSET;
828 self.w
829 }
830}
831#[doc = "Values that can be written to the field `DEM`"]
832pub enum DEMW {
833 #[doc = "DE function is disabled"]
834 DISABLED,
835 #[doc = "The DE signal is output on the RTS pin"]
836 ENABLED,
837}
838impl DEMW {
839 #[allow(missing_docs)]
840 #[doc(hidden)]
841 #[inline]
842 pub fn _bits(&self) -> bool {
843 match *self {
844 DEMW::DISABLED => false,
845 DEMW::ENABLED => true,
846 }
847 }
848}
849#[doc = r" Proxy"]
850pub struct _DEMW<'a> {
851 w: &'a mut W,
852}
853impl<'a> _DEMW<'a> {
854 #[doc = r" Writes `variant` to the field"]
855 #[inline]
856 pub fn variant(self, variant: DEMW) -> &'a mut W {
857 {
858 self.bit(variant._bits())
859 }
860 }
861 #[doc = "DE function is disabled"]
862 #[inline]
863 pub fn disabled(self) -> &'a mut W {
864 self.variant(DEMW::DISABLED)
865 }
866 #[doc = "The DE signal is output on the RTS pin"]
867 #[inline]
868 pub fn enabled(self) -> &'a mut W {
869 self.variant(DEMW::ENABLED)
870 }
871 #[doc = r" Sets the field bit"]
872 pub fn set_bit(self) -> &'a mut W {
873 self.bit(true)
874 }
875 #[doc = r" Clears the field bit"]
876 pub fn clear_bit(self) -> &'a mut W {
877 self.bit(false)
878 }
879 #[doc = r" Writes raw bits to the field"]
880 #[inline]
881 pub fn bit(self, value: bool) -> &'a mut W {
882 const MASK: bool = true;
883 const OFFSET: u8 = 14;
884 self.w.bits &= !((MASK as u32) << OFFSET);
885 self.w.bits |= ((value & MASK) as u32) << OFFSET;
886 self.w
887 }
888}
889#[doc = "Values that can be written to the field `DDRE`"]
890pub enum DDREW {
891 #[doc = "DMA is not disabled in case of reception error"]
892 NOTDISABLED,
893 #[doc = "DMA is disabled following a reception error"]
894 DISABLED,
895}
896impl DDREW {
897 #[allow(missing_docs)]
898 #[doc(hidden)]
899 #[inline]
900 pub fn _bits(&self) -> bool {
901 match *self {
902 DDREW::NOTDISABLED => false,
903 DDREW::DISABLED => true,
904 }
905 }
906}
907#[doc = r" Proxy"]
908pub struct _DDREW<'a> {
909 w: &'a mut W,
910}
911impl<'a> _DDREW<'a> {
912 #[doc = r" Writes `variant` to the field"]
913 #[inline]
914 pub fn variant(self, variant: DDREW) -> &'a mut W {
915 {
916 self.bit(variant._bits())
917 }
918 }
919 #[doc = "DMA is not disabled in case of reception error"]
920 #[inline]
921 pub fn not_disabled(self) -> &'a mut W {
922 self.variant(DDREW::NOTDISABLED)
923 }
924 #[doc = "DMA is disabled following a reception error"]
925 #[inline]
926 pub fn disabled(self) -> &'a mut W {
927 self.variant(DDREW::DISABLED)
928 }
929 #[doc = r" Sets the field bit"]
930 pub fn set_bit(self) -> &'a mut W {
931 self.bit(true)
932 }
933 #[doc = r" Clears the field bit"]
934 pub fn clear_bit(self) -> &'a mut W {
935 self.bit(false)
936 }
937 #[doc = r" Writes raw bits to the field"]
938 #[inline]
939 pub fn bit(self, value: bool) -> &'a mut W {
940 const MASK: bool = true;
941 const OFFSET: u8 = 13;
942 self.w.bits &= !((MASK as u32) << OFFSET);
943 self.w.bits |= ((value & MASK) as u32) << OFFSET;
944 self.w
945 }
946}
947#[doc = "Values that can be written to the field `OVRDIS`"]
948pub enum OVRDISW {
949 #[doc = "Overrun Error Flag, ORE, is set when received data is not read before receiving new data"]
950 ENABLED,
951 #[doc = "Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register"]
952 DISABLED,
953}
954impl OVRDISW {
955 #[allow(missing_docs)]
956 #[doc(hidden)]
957 #[inline]
958 pub fn _bits(&self) -> bool {
959 match *self {
960 OVRDISW::ENABLED => false,
961 OVRDISW::DISABLED => true,
962 }
963 }
964}
965#[doc = r" Proxy"]
966pub struct _OVRDISW<'a> {
967 w: &'a mut W,
968}
969impl<'a> _OVRDISW<'a> {
970 #[doc = r" Writes `variant` to the field"]
971 #[inline]
972 pub fn variant(self, variant: OVRDISW) -> &'a mut W {
973 {
974 self.bit(variant._bits())
975 }
976 }
977 #[doc = "Overrun Error Flag, ORE, is set when received data is not read before receiving new data"]
978 #[inline]
979 pub fn enabled(self) -> &'a mut W {
980 self.variant(OVRDISW::ENABLED)
981 }
982 #[doc = "Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register"]
983 #[inline]
984 pub fn disabled(self) -> &'a mut W {
985 self.variant(OVRDISW::DISABLED)
986 }
987 #[doc = r" Sets the field bit"]
988 pub fn set_bit(self) -> &'a mut W {
989 self.bit(true)
990 }
991 #[doc = r" Clears the field bit"]
992 pub fn clear_bit(self) -> &'a mut W {
993 self.bit(false)
994 }
995 #[doc = r" Writes raw bits to the field"]
996 #[inline]
997 pub fn bit(self, value: bool) -> &'a mut W {
998 const MASK: bool = true;
999 const OFFSET: u8 = 12;
1000 self.w.bits &= !((MASK as u32) << OFFSET);
1001 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1002 self.w
1003 }
1004}
1005#[doc = "Values that can be written to the field `CTSIE`"]
1006pub enum CTSIEW {
1007 #[doc = "Interrupt is inhibited"]
1008 DISABLED,
1009 #[doc = "An interrupt is generated whenever CTSIF=1 in the ISR register"]
1010 ENABLED,
1011}
1012impl CTSIEW {
1013 #[allow(missing_docs)]
1014 #[doc(hidden)]
1015 #[inline]
1016 pub fn _bits(&self) -> bool {
1017 match *self {
1018 CTSIEW::DISABLED => false,
1019 CTSIEW::ENABLED => true,
1020 }
1021 }
1022}
1023#[doc = r" Proxy"]
1024pub struct _CTSIEW<'a> {
1025 w: &'a mut W,
1026}
1027impl<'a> _CTSIEW<'a> {
1028 #[doc = r" Writes `variant` to the field"]
1029 #[inline]
1030 pub fn variant(self, variant: CTSIEW) -> &'a mut W {
1031 {
1032 self.bit(variant._bits())
1033 }
1034 }
1035 #[doc = "Interrupt is inhibited"]
1036 #[inline]
1037 pub fn disabled(self) -> &'a mut W {
1038 self.variant(CTSIEW::DISABLED)
1039 }
1040 #[doc = "An interrupt is generated whenever CTSIF=1 in the ISR register"]
1041 #[inline]
1042 pub fn enabled(self) -> &'a mut W {
1043 self.variant(CTSIEW::ENABLED)
1044 }
1045 #[doc = r" Sets the field bit"]
1046 pub fn set_bit(self) -> &'a mut W {
1047 self.bit(true)
1048 }
1049 #[doc = r" Clears the field bit"]
1050 pub fn clear_bit(self) -> &'a mut W {
1051 self.bit(false)
1052 }
1053 #[doc = r" Writes raw bits to the field"]
1054 #[inline]
1055 pub fn bit(self, value: bool) -> &'a mut W {
1056 const MASK: bool = true;
1057 const OFFSET: u8 = 10;
1058 self.w.bits &= !((MASK as u32) << OFFSET);
1059 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1060 self.w
1061 }
1062}
1063#[doc = "Values that can be written to the field `CTSE`"]
1064pub enum CTSEW {
1065 #[doc = "CTS hardware flow control disabled"]
1066 DISABLED,
1067 #[doc = "CTS mode enabled, data is only transmitted when the CTS input is asserted"]
1068 ENABLED,
1069}
1070impl CTSEW {
1071 #[allow(missing_docs)]
1072 #[doc(hidden)]
1073 #[inline]
1074 pub fn _bits(&self) -> bool {
1075 match *self {
1076 CTSEW::DISABLED => false,
1077 CTSEW::ENABLED => true,
1078 }
1079 }
1080}
1081#[doc = r" Proxy"]
1082pub struct _CTSEW<'a> {
1083 w: &'a mut W,
1084}
1085impl<'a> _CTSEW<'a> {
1086 #[doc = r" Writes `variant` to the field"]
1087 #[inline]
1088 pub fn variant(self, variant: CTSEW) -> &'a mut W {
1089 {
1090 self.bit(variant._bits())
1091 }
1092 }
1093 #[doc = "CTS hardware flow control disabled"]
1094 #[inline]
1095 pub fn disabled(self) -> &'a mut W {
1096 self.variant(CTSEW::DISABLED)
1097 }
1098 #[doc = "CTS mode enabled, data is only transmitted when the CTS input is asserted"]
1099 #[inline]
1100 pub fn enabled(self) -> &'a mut W {
1101 self.variant(CTSEW::ENABLED)
1102 }
1103 #[doc = r" Sets the field bit"]
1104 pub fn set_bit(self) -> &'a mut W {
1105 self.bit(true)
1106 }
1107 #[doc = r" Clears the field bit"]
1108 pub fn clear_bit(self) -> &'a mut W {
1109 self.bit(false)
1110 }
1111 #[doc = r" Writes raw bits to the field"]
1112 #[inline]
1113 pub fn bit(self, value: bool) -> &'a mut W {
1114 const MASK: bool = true;
1115 const OFFSET: u8 = 9;
1116 self.w.bits &= !((MASK as u32) << OFFSET);
1117 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1118 self.w
1119 }
1120}
1121#[doc = "Values that can be written to the field `RTSE`"]
1122pub enum RTSEW {
1123 #[doc = "RTS hardware flow control disabled"]
1124 DISABLED,
1125 #[doc = "RTS output enabled, data is only requested when there is space in the receive buffer"]
1126 ENABLED,
1127}
1128impl RTSEW {
1129 #[allow(missing_docs)]
1130 #[doc(hidden)]
1131 #[inline]
1132 pub fn _bits(&self) -> bool {
1133 match *self {
1134 RTSEW::DISABLED => false,
1135 RTSEW::ENABLED => true,
1136 }
1137 }
1138}
1139#[doc = r" Proxy"]
1140pub struct _RTSEW<'a> {
1141 w: &'a mut W,
1142}
1143impl<'a> _RTSEW<'a> {
1144 #[doc = r" Writes `variant` to the field"]
1145 #[inline]
1146 pub fn variant(self, variant: RTSEW) -> &'a mut W {
1147 {
1148 self.bit(variant._bits())
1149 }
1150 }
1151 #[doc = "RTS hardware flow control disabled"]
1152 #[inline]
1153 pub fn disabled(self) -> &'a mut W {
1154 self.variant(RTSEW::DISABLED)
1155 }
1156 #[doc = "RTS output enabled, data is only requested when there is space in the receive buffer"]
1157 #[inline]
1158 pub fn enabled(self) -> &'a mut W {
1159 self.variant(RTSEW::ENABLED)
1160 }
1161 #[doc = r" Sets the field bit"]
1162 pub fn set_bit(self) -> &'a mut W {
1163 self.bit(true)
1164 }
1165 #[doc = r" Clears the field bit"]
1166 pub fn clear_bit(self) -> &'a mut W {
1167 self.bit(false)
1168 }
1169 #[doc = r" Writes raw bits to the field"]
1170 #[inline]
1171 pub fn bit(self, value: bool) -> &'a mut W {
1172 const MASK: bool = true;
1173 const OFFSET: u8 = 8;
1174 self.w.bits &= !((MASK as u32) << OFFSET);
1175 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1176 self.w
1177 }
1178}
1179#[doc = "Values that can be written to the field `DMAT`"]
1180pub enum DMATW {
1181 #[doc = "DMA mode is disabled for transmission"]
1182 DISABLED,
1183 #[doc = "DMA mode is enabled for transmission"]
1184 ENABLED,
1185}
1186impl DMATW {
1187 #[allow(missing_docs)]
1188 #[doc(hidden)]
1189 #[inline]
1190 pub fn _bits(&self) -> bool {
1191 match *self {
1192 DMATW::DISABLED => false,
1193 DMATW::ENABLED => true,
1194 }
1195 }
1196}
1197#[doc = r" Proxy"]
1198pub struct _DMATW<'a> {
1199 w: &'a mut W,
1200}
1201impl<'a> _DMATW<'a> {
1202 #[doc = r" Writes `variant` to the field"]
1203 #[inline]
1204 pub fn variant(self, variant: DMATW) -> &'a mut W {
1205 {
1206 self.bit(variant._bits())
1207 }
1208 }
1209 #[doc = "DMA mode is disabled for transmission"]
1210 #[inline]
1211 pub fn disabled(self) -> &'a mut W {
1212 self.variant(DMATW::DISABLED)
1213 }
1214 #[doc = "DMA mode is enabled for transmission"]
1215 #[inline]
1216 pub fn enabled(self) -> &'a mut W {
1217 self.variant(DMATW::ENABLED)
1218 }
1219 #[doc = r" Sets the field bit"]
1220 pub fn set_bit(self) -> &'a mut W {
1221 self.bit(true)
1222 }
1223 #[doc = r" Clears the field bit"]
1224 pub fn clear_bit(self) -> &'a mut W {
1225 self.bit(false)
1226 }
1227 #[doc = r" Writes raw bits to the field"]
1228 #[inline]
1229 pub fn bit(self, value: bool) -> &'a mut W {
1230 const MASK: bool = true;
1231 const OFFSET: u8 = 7;
1232 self.w.bits &= !((MASK as u32) << OFFSET);
1233 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1234 self.w
1235 }
1236}
1237#[doc = "Values that can be written to the field `DMAR`"]
1238pub enum DMARW {
1239 #[doc = "DMA mode is disabled for reception"]
1240 DISABLED,
1241 #[doc = "DMA mode is enabled for reception"]
1242 ENABLED,
1243}
1244impl DMARW {
1245 #[allow(missing_docs)]
1246 #[doc(hidden)]
1247 #[inline]
1248 pub fn _bits(&self) -> bool {
1249 match *self {
1250 DMARW::DISABLED => false,
1251 DMARW::ENABLED => true,
1252 }
1253 }
1254}
1255#[doc = r" Proxy"]
1256pub struct _DMARW<'a> {
1257 w: &'a mut W,
1258}
1259impl<'a> _DMARW<'a> {
1260 #[doc = r" Writes `variant` to the field"]
1261 #[inline]
1262 pub fn variant(self, variant: DMARW) -> &'a mut W {
1263 {
1264 self.bit(variant._bits())
1265 }
1266 }
1267 #[doc = "DMA mode is disabled for reception"]
1268 #[inline]
1269 pub fn disabled(self) -> &'a mut W {
1270 self.variant(DMARW::DISABLED)
1271 }
1272 #[doc = "DMA mode is enabled for reception"]
1273 #[inline]
1274 pub fn enabled(self) -> &'a mut W {
1275 self.variant(DMARW::ENABLED)
1276 }
1277 #[doc = r" Sets the field bit"]
1278 pub fn set_bit(self) -> &'a mut W {
1279 self.bit(true)
1280 }
1281 #[doc = r" Clears the field bit"]
1282 pub fn clear_bit(self) -> &'a mut W {
1283 self.bit(false)
1284 }
1285 #[doc = r" Writes raw bits to the field"]
1286 #[inline]
1287 pub fn bit(self, value: bool) -> &'a mut W {
1288 const MASK: bool = true;
1289 const OFFSET: u8 = 6;
1290 self.w.bits &= !((MASK as u32) << OFFSET);
1291 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1292 self.w
1293 }
1294}
1295#[doc = "Values that can be written to the field `HDSEL`"]
1296pub enum HDSELW {
1297 #[doc = "Half duplex mode is not selected"]
1298 NOTSELECTED,
1299 #[doc = "Half duplex mode is selected"]
1300 SELECTED,
1301}
1302impl HDSELW {
1303 #[allow(missing_docs)]
1304 #[doc(hidden)]
1305 #[inline]
1306 pub fn _bits(&self) -> bool {
1307 match *self {
1308 HDSELW::NOTSELECTED => false,
1309 HDSELW::SELECTED => true,
1310 }
1311 }
1312}
1313#[doc = r" Proxy"]
1314pub struct _HDSELW<'a> {
1315 w: &'a mut W,
1316}
1317impl<'a> _HDSELW<'a> {
1318 #[doc = r" Writes `variant` to the field"]
1319 #[inline]
1320 pub fn variant(self, variant: HDSELW) -> &'a mut W {
1321 {
1322 self.bit(variant._bits())
1323 }
1324 }
1325 #[doc = "Half duplex mode is not selected"]
1326 #[inline]
1327 pub fn not_selected(self) -> &'a mut W {
1328 self.variant(HDSELW::NOTSELECTED)
1329 }
1330 #[doc = "Half duplex mode is selected"]
1331 #[inline]
1332 pub fn selected(self) -> &'a mut W {
1333 self.variant(HDSELW::SELECTED)
1334 }
1335 #[doc = r" Sets the field bit"]
1336 pub fn set_bit(self) -> &'a mut W {
1337 self.bit(true)
1338 }
1339 #[doc = r" Clears the field bit"]
1340 pub fn clear_bit(self) -> &'a mut W {
1341 self.bit(false)
1342 }
1343 #[doc = r" Writes raw bits to the field"]
1344 #[inline]
1345 pub fn bit(self, value: bool) -> &'a mut W {
1346 const MASK: bool = true;
1347 const OFFSET: u8 = 3;
1348 self.w.bits &= !((MASK as u32) << OFFSET);
1349 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1350 self.w
1351 }
1352}
1353#[doc = "Values that can be written to the field `EIE`"]
1354pub enum EIEW {
1355 #[doc = "Interrupt is inhibited"]
1356 DISABLED,
1357 #[doc = "An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register"]
1358 ENABLED,
1359}
1360impl EIEW {
1361 #[allow(missing_docs)]
1362 #[doc(hidden)]
1363 #[inline]
1364 pub fn _bits(&self) -> bool {
1365 match *self {
1366 EIEW::DISABLED => false,
1367 EIEW::ENABLED => true,
1368 }
1369 }
1370}
1371#[doc = r" Proxy"]
1372pub struct _EIEW<'a> {
1373 w: &'a mut W,
1374}
1375impl<'a> _EIEW<'a> {
1376 #[doc = r" Writes `variant` to the field"]
1377 #[inline]
1378 pub fn variant(self, variant: EIEW) -> &'a mut W {
1379 {
1380 self.bit(variant._bits())
1381 }
1382 }
1383 #[doc = "Interrupt is inhibited"]
1384 #[inline]
1385 pub fn disabled(self) -> &'a mut W {
1386 self.variant(EIEW::DISABLED)
1387 }
1388 #[doc = "An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register"]
1389 #[inline]
1390 pub fn enabled(self) -> &'a mut W {
1391 self.variant(EIEW::ENABLED)
1392 }
1393 #[doc = r" Sets the field bit"]
1394 pub fn set_bit(self) -> &'a mut W {
1395 self.bit(true)
1396 }
1397 #[doc = r" Clears the field bit"]
1398 pub fn clear_bit(self) -> &'a mut W {
1399 self.bit(false)
1400 }
1401 #[doc = r" Writes raw bits to the field"]
1402 #[inline]
1403 pub fn bit(self, value: bool) -> &'a mut W {
1404 const MASK: bool = true;
1405 const OFFSET: u8 = 0;
1406 self.w.bits &= !((MASK as u32) << OFFSET);
1407 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1408 self.w
1409 }
1410}
1411impl R {
1412 #[doc = r" Value of the register as raw bits"]
1413 #[inline]
1414 pub fn bits(&self) -> u32 {
1415 self.bits
1416 }
1417 #[doc = "Bit 22 - Wakeup from Stop mode interrupt enable"]
1418 #[inline]
1419 pub fn wufie(&self) -> WUFIER {
1420 WUFIER::_from({
1421 const MASK: bool = true;
1422 const OFFSET: u8 = 22;
1423 ((self.bits >> OFFSET) & MASK as u32) != 0
1424 })
1425 }
1426 #[doc = "Bits 20:21 - Wakeup from Stop mode interrupt flag selection"]
1427 #[inline]
1428 pub fn wus(&self) -> WUSR {
1429 WUSR::_from({
1430 const MASK: u8 = 3;
1431 const OFFSET: u8 = 20;
1432 ((self.bits >> OFFSET) & MASK as u32) as u8
1433 })
1434 }
1435 #[doc = "Bit 15 - Driver enable polarity selection"]
1436 #[inline]
1437 pub fn dep(&self) -> DEPR {
1438 DEPR::_from({
1439 const MASK: bool = true;
1440 const OFFSET: u8 = 15;
1441 ((self.bits >> OFFSET) & MASK as u32) != 0
1442 })
1443 }
1444 #[doc = "Bit 14 - Driver enable mode"]
1445 #[inline]
1446 pub fn dem(&self) -> DEMR {
1447 DEMR::_from({
1448 const MASK: bool = true;
1449 const OFFSET: u8 = 14;
1450 ((self.bits >> OFFSET) & MASK as u32) != 0
1451 })
1452 }
1453 #[doc = "Bit 13 - DMA Disable on Reception Error"]
1454 #[inline]
1455 pub fn ddre(&self) -> DDRER {
1456 DDRER::_from({
1457 const MASK: bool = true;
1458 const OFFSET: u8 = 13;
1459 ((self.bits >> OFFSET) & MASK as u32) != 0
1460 })
1461 }
1462 #[doc = "Bit 12 - Overrun Disable"]
1463 #[inline]
1464 pub fn ovrdis(&self) -> OVRDISR {
1465 OVRDISR::_from({
1466 const MASK: bool = true;
1467 const OFFSET: u8 = 12;
1468 ((self.bits >> OFFSET) & MASK as u32) != 0
1469 })
1470 }
1471 #[doc = "Bit 10 - CTS interrupt enable"]
1472 #[inline]
1473 pub fn ctsie(&self) -> CTSIER {
1474 CTSIER::_from({
1475 const MASK: bool = true;
1476 const OFFSET: u8 = 10;
1477 ((self.bits >> OFFSET) & MASK as u32) != 0
1478 })
1479 }
1480 #[doc = "Bit 9 - CTS enable"]
1481 #[inline]
1482 pub fn ctse(&self) -> CTSER {
1483 CTSER::_from({
1484 const MASK: bool = true;
1485 const OFFSET: u8 = 9;
1486 ((self.bits >> OFFSET) & MASK as u32) != 0
1487 })
1488 }
1489 #[doc = "Bit 8 - RTS enable"]
1490 #[inline]
1491 pub fn rtse(&self) -> RTSER {
1492 RTSER::_from({
1493 const MASK: bool = true;
1494 const OFFSET: u8 = 8;
1495 ((self.bits >> OFFSET) & MASK as u32) != 0
1496 })
1497 }
1498 #[doc = "Bit 7 - DMA enable transmitter"]
1499 #[inline]
1500 pub fn dmat(&self) -> DMATR {
1501 DMATR::_from({
1502 const MASK: bool = true;
1503 const OFFSET: u8 = 7;
1504 ((self.bits >> OFFSET) & MASK as u32) != 0
1505 })
1506 }
1507 #[doc = "Bit 6 - DMA enable receiver"]
1508 #[inline]
1509 pub fn dmar(&self) -> DMARR {
1510 DMARR::_from({
1511 const MASK: bool = true;
1512 const OFFSET: u8 = 6;
1513 ((self.bits >> OFFSET) & MASK as u32) != 0
1514 })
1515 }
1516 #[doc = "Bit 3 - Half-duplex selection"]
1517 #[inline]
1518 pub fn hdsel(&self) -> HDSELR {
1519 HDSELR::_from({
1520 const MASK: bool = true;
1521 const OFFSET: u8 = 3;
1522 ((self.bits >> OFFSET) & MASK as u32) != 0
1523 })
1524 }
1525 #[doc = "Bit 0 - Error interrupt enable"]
1526 #[inline]
1527 pub fn eie(&self) -> EIER {
1528 EIER::_from({
1529 const MASK: bool = true;
1530 const OFFSET: u8 = 0;
1531 ((self.bits >> OFFSET) & MASK as u32) != 0
1532 })
1533 }
1534}
1535impl W {
1536 #[doc = r" Reset value of the register"]
1537 #[inline]
1538 pub fn reset_value() -> W {
1539 W { bits: 0 }
1540 }
1541 #[doc = r" Writes raw bits to the register"]
1542 #[inline]
1543 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1544 self.bits = bits;
1545 self
1546 }
1547 #[doc = "Bit 22 - Wakeup from Stop mode interrupt enable"]
1548 #[inline]
1549 pub fn wufie(&mut self) -> _WUFIEW {
1550 _WUFIEW { w: self }
1551 }
1552 #[doc = "Bits 20:21 - Wakeup from Stop mode interrupt flag selection"]
1553 #[inline]
1554 pub fn wus(&mut self) -> _WUSW {
1555 _WUSW { w: self }
1556 }
1557 #[doc = "Bit 15 - Driver enable polarity selection"]
1558 #[inline]
1559 pub fn dep(&mut self) -> _DEPW {
1560 _DEPW { w: self }
1561 }
1562 #[doc = "Bit 14 - Driver enable mode"]
1563 #[inline]
1564 pub fn dem(&mut self) -> _DEMW {
1565 _DEMW { w: self }
1566 }
1567 #[doc = "Bit 13 - DMA Disable on Reception Error"]
1568 #[inline]
1569 pub fn ddre(&mut self) -> _DDREW {
1570 _DDREW { w: self }
1571 }
1572 #[doc = "Bit 12 - Overrun Disable"]
1573 #[inline]
1574 pub fn ovrdis(&mut self) -> _OVRDISW {
1575 _OVRDISW { w: self }
1576 }
1577 #[doc = "Bit 10 - CTS interrupt enable"]
1578 #[inline]
1579 pub fn ctsie(&mut self) -> _CTSIEW {
1580 _CTSIEW { w: self }
1581 }
1582 #[doc = "Bit 9 - CTS enable"]
1583 #[inline]
1584 pub fn ctse(&mut self) -> _CTSEW {
1585 _CTSEW { w: self }
1586 }
1587 #[doc = "Bit 8 - RTS enable"]
1588 #[inline]
1589 pub fn rtse(&mut self) -> _RTSEW {
1590 _RTSEW { w: self }
1591 }
1592 #[doc = "Bit 7 - DMA enable transmitter"]
1593 #[inline]
1594 pub fn dmat(&mut self) -> _DMATW {
1595 _DMATW { w: self }
1596 }
1597 #[doc = "Bit 6 - DMA enable receiver"]
1598 #[inline]
1599 pub fn dmar(&mut self) -> _DMARW {
1600 _DMARW { w: self }
1601 }
1602 #[doc = "Bit 3 - Half-duplex selection"]
1603 #[inline]
1604 pub fn hdsel(&mut self) -> _HDSELW {
1605 _HDSELW { w: self }
1606 }
1607 #[doc = "Bit 0 - Error interrupt enable"]
1608 #[inline]
1609 pub fn eie(&mut self) -> _EIEW {
1610 _EIEW { w: self }
1611 }
1612}