1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::CR2 {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = "Possible values of the field `MSBFIRST`"]
46#[derive(Clone, Copy, Debug, PartialEq)]
47pub enum MSBFIRSTR {
48 #[doc = "data is transmitted/received with data bit 0 first, following the start bit"]
49 LSB,
50 #[doc = "data is transmitted/received with MSB (bit 7/8/9) first, following the start bit"]
51 MSB,
52}
53impl MSBFIRSTR {
54 #[doc = r" Returns `true` if the bit is clear (0)"]
55 #[inline]
56 pub fn bit_is_clear(&self) -> bool {
57 !self.bit()
58 }
59 #[doc = r" Returns `true` if the bit is set (1)"]
60 #[inline]
61 pub fn bit_is_set(&self) -> bool {
62 self.bit()
63 }
64 #[doc = r" Value of the field as raw bits"]
65 #[inline]
66 pub fn bit(&self) -> bool {
67 match *self {
68 MSBFIRSTR::LSB => false,
69 MSBFIRSTR::MSB => true,
70 }
71 }
72 #[allow(missing_docs)]
73 #[doc(hidden)]
74 #[inline]
75 pub fn _from(value: bool) -> MSBFIRSTR {
76 match value {
77 false => MSBFIRSTR::LSB,
78 true => MSBFIRSTR::MSB,
79 }
80 }
81 #[doc = "Checks if the value of the field is `LSB`"]
82 #[inline]
83 pub fn is_lsb(&self) -> bool {
84 *self == MSBFIRSTR::LSB
85 }
86 #[doc = "Checks if the value of the field is `MSB`"]
87 #[inline]
88 pub fn is_msb(&self) -> bool {
89 *self == MSBFIRSTR::MSB
90 }
91}
92#[doc = "Possible values of the field `DATAINV`"]
93#[derive(Clone, Copy, Debug, PartialEq)]
94pub enum DATAINVR {
95 #[doc = "Logical data from the data register are send/received in positive/direct logic"]
96 POSITIVE,
97 #[doc = "Logical data from the data register are send/received in negative/inverse logic"]
98 NEGATIVE,
99}
100impl DATAINVR {
101 #[doc = r" Returns `true` if the bit is clear (0)"]
102 #[inline]
103 pub fn bit_is_clear(&self) -> bool {
104 !self.bit()
105 }
106 #[doc = r" Returns `true` if the bit is set (1)"]
107 #[inline]
108 pub fn bit_is_set(&self) -> bool {
109 self.bit()
110 }
111 #[doc = r" Value of the field as raw bits"]
112 #[inline]
113 pub fn bit(&self) -> bool {
114 match *self {
115 DATAINVR::POSITIVE => false,
116 DATAINVR::NEGATIVE => true,
117 }
118 }
119 #[allow(missing_docs)]
120 #[doc(hidden)]
121 #[inline]
122 pub fn _from(value: bool) -> DATAINVR {
123 match value {
124 false => DATAINVR::POSITIVE,
125 true => DATAINVR::NEGATIVE,
126 }
127 }
128 #[doc = "Checks if the value of the field is `POSITIVE`"]
129 #[inline]
130 pub fn is_positive(&self) -> bool {
131 *self == DATAINVR::POSITIVE
132 }
133 #[doc = "Checks if the value of the field is `NEGATIVE`"]
134 #[inline]
135 pub fn is_negative(&self) -> bool {
136 *self == DATAINVR::NEGATIVE
137 }
138}
139#[doc = "Possible values of the field `TXINV`"]
140#[derive(Clone, Copy, Debug, PartialEq)]
141pub enum TXINVR {
142 #[doc = "TX pin signal works using the standard logic levels"]
143 STANDARD,
144 #[doc = "TX pin signal values are inverted"]
145 INVERTED,
146}
147impl TXINVR {
148 #[doc = r" Returns `true` if the bit is clear (0)"]
149 #[inline]
150 pub fn bit_is_clear(&self) -> bool {
151 !self.bit()
152 }
153 #[doc = r" Returns `true` if the bit is set (1)"]
154 #[inline]
155 pub fn bit_is_set(&self) -> bool {
156 self.bit()
157 }
158 #[doc = r" Value of the field as raw bits"]
159 #[inline]
160 pub fn bit(&self) -> bool {
161 match *self {
162 TXINVR::STANDARD => false,
163 TXINVR::INVERTED => true,
164 }
165 }
166 #[allow(missing_docs)]
167 #[doc(hidden)]
168 #[inline]
169 pub fn _from(value: bool) -> TXINVR {
170 match value {
171 false => TXINVR::STANDARD,
172 true => TXINVR::INVERTED,
173 }
174 }
175 #[doc = "Checks if the value of the field is `STANDARD`"]
176 #[inline]
177 pub fn is_standard(&self) -> bool {
178 *self == TXINVR::STANDARD
179 }
180 #[doc = "Checks if the value of the field is `INVERTED`"]
181 #[inline]
182 pub fn is_inverted(&self) -> bool {
183 *self == TXINVR::INVERTED
184 }
185}
186#[doc = "Possible values of the field `RXINV`"]
187#[derive(Clone, Copy, Debug, PartialEq)]
188pub enum RXINVR {
189 #[doc = "RX pin signal works using the standard logic levels"]
190 STANDARD,
191 #[doc = "RX pin signal values are inverted"]
192 INVERTED,
193}
194impl RXINVR {
195 #[doc = r" Returns `true` if the bit is clear (0)"]
196 #[inline]
197 pub fn bit_is_clear(&self) -> bool {
198 !self.bit()
199 }
200 #[doc = r" Returns `true` if the bit is set (1)"]
201 #[inline]
202 pub fn bit_is_set(&self) -> bool {
203 self.bit()
204 }
205 #[doc = r" Value of the field as raw bits"]
206 #[inline]
207 pub fn bit(&self) -> bool {
208 match *self {
209 RXINVR::STANDARD => false,
210 RXINVR::INVERTED => true,
211 }
212 }
213 #[allow(missing_docs)]
214 #[doc(hidden)]
215 #[inline]
216 pub fn _from(value: bool) -> RXINVR {
217 match value {
218 false => RXINVR::STANDARD,
219 true => RXINVR::INVERTED,
220 }
221 }
222 #[doc = "Checks if the value of the field is `STANDARD`"]
223 #[inline]
224 pub fn is_standard(&self) -> bool {
225 *self == RXINVR::STANDARD
226 }
227 #[doc = "Checks if the value of the field is `INVERTED`"]
228 #[inline]
229 pub fn is_inverted(&self) -> bool {
230 *self == RXINVR::INVERTED
231 }
232}
233#[doc = "Possible values of the field `SWAP`"]
234#[derive(Clone, Copy, Debug, PartialEq)]
235pub enum SWAPR {
236 #[doc = "TX/RX pins are used as defined in standard pinout"]
237 STANDARD,
238 #[doc = "The TX and RX pins functions are swapped"]
239 SWAPPED,
240}
241impl SWAPR {
242 #[doc = r" Returns `true` if the bit is clear (0)"]
243 #[inline]
244 pub fn bit_is_clear(&self) -> bool {
245 !self.bit()
246 }
247 #[doc = r" Returns `true` if the bit is set (1)"]
248 #[inline]
249 pub fn bit_is_set(&self) -> bool {
250 self.bit()
251 }
252 #[doc = r" Value of the field as raw bits"]
253 #[inline]
254 pub fn bit(&self) -> bool {
255 match *self {
256 SWAPR::STANDARD => false,
257 SWAPR::SWAPPED => true,
258 }
259 }
260 #[allow(missing_docs)]
261 #[doc(hidden)]
262 #[inline]
263 pub fn _from(value: bool) -> SWAPR {
264 match value {
265 false => SWAPR::STANDARD,
266 true => SWAPR::SWAPPED,
267 }
268 }
269 #[doc = "Checks if the value of the field is `STANDARD`"]
270 #[inline]
271 pub fn is_standard(&self) -> bool {
272 *self == SWAPR::STANDARD
273 }
274 #[doc = "Checks if the value of the field is `SWAPPED`"]
275 #[inline]
276 pub fn is_swapped(&self) -> bool {
277 *self == SWAPR::SWAPPED
278 }
279}
280#[doc = "Possible values of the field `STOP`"]
281#[derive(Clone, Copy, Debug, PartialEq)]
282pub enum STOPR {
283 #[doc = "1 stop bit"]
284 STOP1,
285 #[doc = "0.5 stop bit"]
286 STOP0P5,
287 #[doc = "2 stop bit"]
288 STOP2,
289 #[doc = "1.5 stop bit"]
290 STOP1P5,
291}
292impl STOPR {
293 #[doc = r" Value of the field as raw bits"]
294 #[inline]
295 pub fn bits(&self) -> u8 {
296 match *self {
297 STOPR::STOP1 => 0,
298 STOPR::STOP0P5 => 1,
299 STOPR::STOP2 => 2,
300 STOPR::STOP1P5 => 3,
301 }
302 }
303 #[allow(missing_docs)]
304 #[doc(hidden)]
305 #[inline]
306 pub fn _from(value: u8) -> STOPR {
307 match value {
308 0 => STOPR::STOP1,
309 1 => STOPR::STOP0P5,
310 2 => STOPR::STOP2,
311 3 => STOPR::STOP1P5,
312 _ => unreachable!(),
313 }
314 }
315 #[doc = "Checks if the value of the field is `STOP1`"]
316 #[inline]
317 pub fn is_stop1(&self) -> bool {
318 *self == STOPR::STOP1
319 }
320 #[doc = "Checks if the value of the field is `STOP0P5`"]
321 #[inline]
322 pub fn is_stop0p5(&self) -> bool {
323 *self == STOPR::STOP0P5
324 }
325 #[doc = "Checks if the value of the field is `STOP2`"]
326 #[inline]
327 pub fn is_stop2(&self) -> bool {
328 *self == STOPR::STOP2
329 }
330 #[doc = "Checks if the value of the field is `STOP1P5`"]
331 #[inline]
332 pub fn is_stop1p5(&self) -> bool {
333 *self == STOPR::STOP1P5
334 }
335}
336#[doc = "Possible values of the field `CLKEN`"]
337#[derive(Clone, Copy, Debug, PartialEq)]
338pub enum CLKENR {
339 #[doc = "CK pin disabled"]
340 DISABLED,
341 #[doc = "CK pin enabled"]
342 ENABLED,
343}
344impl CLKENR {
345 #[doc = r" Returns `true` if the bit is clear (0)"]
346 #[inline]
347 pub fn bit_is_clear(&self) -> bool {
348 !self.bit()
349 }
350 #[doc = r" Returns `true` if the bit is set (1)"]
351 #[inline]
352 pub fn bit_is_set(&self) -> bool {
353 self.bit()
354 }
355 #[doc = r" Value of the field as raw bits"]
356 #[inline]
357 pub fn bit(&self) -> bool {
358 match *self {
359 CLKENR::DISABLED => false,
360 CLKENR::ENABLED => true,
361 }
362 }
363 #[allow(missing_docs)]
364 #[doc(hidden)]
365 #[inline]
366 pub fn _from(value: bool) -> CLKENR {
367 match value {
368 false => CLKENR::DISABLED,
369 true => CLKENR::ENABLED,
370 }
371 }
372 #[doc = "Checks if the value of the field is `DISABLED`"]
373 #[inline]
374 pub fn is_disabled(&self) -> bool {
375 *self == CLKENR::DISABLED
376 }
377 #[doc = "Checks if the value of the field is `ENABLED`"]
378 #[inline]
379 pub fn is_enabled(&self) -> bool {
380 *self == CLKENR::ENABLED
381 }
382}
383#[doc = "Possible values of the field `ADDM7`"]
384#[derive(Clone, Copy, Debug, PartialEq)]
385pub enum ADDM7R {
386 #[doc = "4-bit address detection"]
387 BIT4,
388 #[doc = "7-bit address detection"]
389 BIT7,
390}
391impl ADDM7R {
392 #[doc = r" Returns `true` if the bit is clear (0)"]
393 #[inline]
394 pub fn bit_is_clear(&self) -> bool {
395 !self.bit()
396 }
397 #[doc = r" Returns `true` if the bit is set (1)"]
398 #[inline]
399 pub fn bit_is_set(&self) -> bool {
400 self.bit()
401 }
402 #[doc = r" Value of the field as raw bits"]
403 #[inline]
404 pub fn bit(&self) -> bool {
405 match *self {
406 ADDM7R::BIT4 => false,
407 ADDM7R::BIT7 => true,
408 }
409 }
410 #[allow(missing_docs)]
411 #[doc(hidden)]
412 #[inline]
413 pub fn _from(value: bool) -> ADDM7R {
414 match value {
415 false => ADDM7R::BIT4,
416 true => ADDM7R::BIT7,
417 }
418 }
419 #[doc = "Checks if the value of the field is `BIT4`"]
420 #[inline]
421 pub fn is_bit4(&self) -> bool {
422 *self == ADDM7R::BIT4
423 }
424 #[doc = "Checks if the value of the field is `BIT7`"]
425 #[inline]
426 pub fn is_bit7(&self) -> bool {
427 *self == ADDM7R::BIT7
428 }
429}
430#[doc = r" Value of the field"]
431pub struct ADDR {
432 bits: u8,
433}
434impl ADDR {
435 #[doc = r" Value of the field as raw bits"]
436 #[inline]
437 pub fn bits(&self) -> u8 {
438 self.bits
439 }
440}
441#[doc = "Values that can be written to the field `MSBFIRST`"]
442pub enum MSBFIRSTW {
443 #[doc = "data is transmitted/received with data bit 0 first, following the start bit"]
444 LSB,
445 #[doc = "data is transmitted/received with MSB (bit 7/8/9) first, following the start bit"]
446 MSB,
447}
448impl MSBFIRSTW {
449 #[allow(missing_docs)]
450 #[doc(hidden)]
451 #[inline]
452 pub fn _bits(&self) -> bool {
453 match *self {
454 MSBFIRSTW::LSB => false,
455 MSBFIRSTW::MSB => true,
456 }
457 }
458}
459#[doc = r" Proxy"]
460pub struct _MSBFIRSTW<'a> {
461 w: &'a mut W,
462}
463impl<'a> _MSBFIRSTW<'a> {
464 #[doc = r" Writes `variant` to the field"]
465 #[inline]
466 pub fn variant(self, variant: MSBFIRSTW) -> &'a mut W {
467 {
468 self.bit(variant._bits())
469 }
470 }
471 #[doc = "data is transmitted/received with data bit 0 first, following the start bit"]
472 #[inline]
473 pub fn lsb(self) -> &'a mut W {
474 self.variant(MSBFIRSTW::LSB)
475 }
476 #[doc = "data is transmitted/received with MSB (bit 7/8/9) first, following the start bit"]
477 #[inline]
478 pub fn msb(self) -> &'a mut W {
479 self.variant(MSBFIRSTW::MSB)
480 }
481 #[doc = r" Sets the field bit"]
482 pub fn set_bit(self) -> &'a mut W {
483 self.bit(true)
484 }
485 #[doc = r" Clears the field bit"]
486 pub fn clear_bit(self) -> &'a mut W {
487 self.bit(false)
488 }
489 #[doc = r" Writes raw bits to the field"]
490 #[inline]
491 pub fn bit(self, value: bool) -> &'a mut W {
492 const MASK: bool = true;
493 const OFFSET: u8 = 19;
494 self.w.bits &= !((MASK as u32) << OFFSET);
495 self.w.bits |= ((value & MASK) as u32) << OFFSET;
496 self.w
497 }
498}
499#[doc = "Values that can be written to the field `DATAINV`"]
500pub enum DATAINVW {
501 #[doc = "Logical data from the data register are send/received in positive/direct logic"]
502 POSITIVE,
503 #[doc = "Logical data from the data register are send/received in negative/inverse logic"]
504 NEGATIVE,
505}
506impl DATAINVW {
507 #[allow(missing_docs)]
508 #[doc(hidden)]
509 #[inline]
510 pub fn _bits(&self) -> bool {
511 match *self {
512 DATAINVW::POSITIVE => false,
513 DATAINVW::NEGATIVE => true,
514 }
515 }
516}
517#[doc = r" Proxy"]
518pub struct _DATAINVW<'a> {
519 w: &'a mut W,
520}
521impl<'a> _DATAINVW<'a> {
522 #[doc = r" Writes `variant` to the field"]
523 #[inline]
524 pub fn variant(self, variant: DATAINVW) -> &'a mut W {
525 {
526 self.bit(variant._bits())
527 }
528 }
529 #[doc = "Logical data from the data register are send/received in positive/direct logic"]
530 #[inline]
531 pub fn positive(self) -> &'a mut W {
532 self.variant(DATAINVW::POSITIVE)
533 }
534 #[doc = "Logical data from the data register are send/received in negative/inverse logic"]
535 #[inline]
536 pub fn negative(self) -> &'a mut W {
537 self.variant(DATAINVW::NEGATIVE)
538 }
539 #[doc = r" Sets the field bit"]
540 pub fn set_bit(self) -> &'a mut W {
541 self.bit(true)
542 }
543 #[doc = r" Clears the field bit"]
544 pub fn clear_bit(self) -> &'a mut W {
545 self.bit(false)
546 }
547 #[doc = r" Writes raw bits to the field"]
548 #[inline]
549 pub fn bit(self, value: bool) -> &'a mut W {
550 const MASK: bool = true;
551 const OFFSET: u8 = 18;
552 self.w.bits &= !((MASK as u32) << OFFSET);
553 self.w.bits |= ((value & MASK) as u32) << OFFSET;
554 self.w
555 }
556}
557#[doc = "Values that can be written to the field `TXINV`"]
558pub enum TXINVW {
559 #[doc = "TX pin signal works using the standard logic levels"]
560 STANDARD,
561 #[doc = "TX pin signal values are inverted"]
562 INVERTED,
563}
564impl TXINVW {
565 #[allow(missing_docs)]
566 #[doc(hidden)]
567 #[inline]
568 pub fn _bits(&self) -> bool {
569 match *self {
570 TXINVW::STANDARD => false,
571 TXINVW::INVERTED => true,
572 }
573 }
574}
575#[doc = r" Proxy"]
576pub struct _TXINVW<'a> {
577 w: &'a mut W,
578}
579impl<'a> _TXINVW<'a> {
580 #[doc = r" Writes `variant` to the field"]
581 #[inline]
582 pub fn variant(self, variant: TXINVW) -> &'a mut W {
583 {
584 self.bit(variant._bits())
585 }
586 }
587 #[doc = "TX pin signal works using the standard logic levels"]
588 #[inline]
589 pub fn standard(self) -> &'a mut W {
590 self.variant(TXINVW::STANDARD)
591 }
592 #[doc = "TX pin signal values are inverted"]
593 #[inline]
594 pub fn inverted(self) -> &'a mut W {
595 self.variant(TXINVW::INVERTED)
596 }
597 #[doc = r" Sets the field bit"]
598 pub fn set_bit(self) -> &'a mut W {
599 self.bit(true)
600 }
601 #[doc = r" Clears the field bit"]
602 pub fn clear_bit(self) -> &'a mut W {
603 self.bit(false)
604 }
605 #[doc = r" Writes raw bits to the field"]
606 #[inline]
607 pub fn bit(self, value: bool) -> &'a mut W {
608 const MASK: bool = true;
609 const OFFSET: u8 = 17;
610 self.w.bits &= !((MASK as u32) << OFFSET);
611 self.w.bits |= ((value & MASK) as u32) << OFFSET;
612 self.w
613 }
614}
615#[doc = "Values that can be written to the field `RXINV`"]
616pub enum RXINVW {
617 #[doc = "RX pin signal works using the standard logic levels"]
618 STANDARD,
619 #[doc = "RX pin signal values are inverted"]
620 INVERTED,
621}
622impl RXINVW {
623 #[allow(missing_docs)]
624 #[doc(hidden)]
625 #[inline]
626 pub fn _bits(&self) -> bool {
627 match *self {
628 RXINVW::STANDARD => false,
629 RXINVW::INVERTED => true,
630 }
631 }
632}
633#[doc = r" Proxy"]
634pub struct _RXINVW<'a> {
635 w: &'a mut W,
636}
637impl<'a> _RXINVW<'a> {
638 #[doc = r" Writes `variant` to the field"]
639 #[inline]
640 pub fn variant(self, variant: RXINVW) -> &'a mut W {
641 {
642 self.bit(variant._bits())
643 }
644 }
645 #[doc = "RX pin signal works using the standard logic levels"]
646 #[inline]
647 pub fn standard(self) -> &'a mut W {
648 self.variant(RXINVW::STANDARD)
649 }
650 #[doc = "RX pin signal values are inverted"]
651 #[inline]
652 pub fn inverted(self) -> &'a mut W {
653 self.variant(RXINVW::INVERTED)
654 }
655 #[doc = r" Sets the field bit"]
656 pub fn set_bit(self) -> &'a mut W {
657 self.bit(true)
658 }
659 #[doc = r" Clears the field bit"]
660 pub fn clear_bit(self) -> &'a mut W {
661 self.bit(false)
662 }
663 #[doc = r" Writes raw bits to the field"]
664 #[inline]
665 pub fn bit(self, value: bool) -> &'a mut W {
666 const MASK: bool = true;
667 const OFFSET: u8 = 16;
668 self.w.bits &= !((MASK as u32) << OFFSET);
669 self.w.bits |= ((value & MASK) as u32) << OFFSET;
670 self.w
671 }
672}
673#[doc = "Values that can be written to the field `SWAP`"]
674pub enum SWAPW {
675 #[doc = "TX/RX pins are used as defined in standard pinout"]
676 STANDARD,
677 #[doc = "The TX and RX pins functions are swapped"]
678 SWAPPED,
679}
680impl SWAPW {
681 #[allow(missing_docs)]
682 #[doc(hidden)]
683 #[inline]
684 pub fn _bits(&self) -> bool {
685 match *self {
686 SWAPW::STANDARD => false,
687 SWAPW::SWAPPED => true,
688 }
689 }
690}
691#[doc = r" Proxy"]
692pub struct _SWAPW<'a> {
693 w: &'a mut W,
694}
695impl<'a> _SWAPW<'a> {
696 #[doc = r" Writes `variant` to the field"]
697 #[inline]
698 pub fn variant(self, variant: SWAPW) -> &'a mut W {
699 {
700 self.bit(variant._bits())
701 }
702 }
703 #[doc = "TX/RX pins are used as defined in standard pinout"]
704 #[inline]
705 pub fn standard(self) -> &'a mut W {
706 self.variant(SWAPW::STANDARD)
707 }
708 #[doc = "The TX and RX pins functions are swapped"]
709 #[inline]
710 pub fn swapped(self) -> &'a mut W {
711 self.variant(SWAPW::SWAPPED)
712 }
713 #[doc = r" Sets the field bit"]
714 pub fn set_bit(self) -> &'a mut W {
715 self.bit(true)
716 }
717 #[doc = r" Clears the field bit"]
718 pub fn clear_bit(self) -> &'a mut W {
719 self.bit(false)
720 }
721 #[doc = r" Writes raw bits to the field"]
722 #[inline]
723 pub fn bit(self, value: bool) -> &'a mut W {
724 const MASK: bool = true;
725 const OFFSET: u8 = 15;
726 self.w.bits &= !((MASK as u32) << OFFSET);
727 self.w.bits |= ((value & MASK) as u32) << OFFSET;
728 self.w
729 }
730}
731#[doc = "Values that can be written to the field `STOP`"]
732pub enum STOPW {
733 #[doc = "1 stop bit"]
734 STOP1,
735 #[doc = "0.5 stop bit"]
736 STOP0P5,
737 #[doc = "2 stop bit"]
738 STOP2,
739 #[doc = "1.5 stop bit"]
740 STOP1P5,
741}
742impl STOPW {
743 #[allow(missing_docs)]
744 #[doc(hidden)]
745 #[inline]
746 pub fn _bits(&self) -> u8 {
747 match *self {
748 STOPW::STOP1 => 0,
749 STOPW::STOP0P5 => 1,
750 STOPW::STOP2 => 2,
751 STOPW::STOP1P5 => 3,
752 }
753 }
754}
755#[doc = r" Proxy"]
756pub struct _STOPW<'a> {
757 w: &'a mut W,
758}
759impl<'a> _STOPW<'a> {
760 #[doc = r" Writes `variant` to the field"]
761 #[inline]
762 pub fn variant(self, variant: STOPW) -> &'a mut W {
763 {
764 self.bits(variant._bits())
765 }
766 }
767 #[doc = "1 stop bit"]
768 #[inline]
769 pub fn stop1(self) -> &'a mut W {
770 self.variant(STOPW::STOP1)
771 }
772 #[doc = "0.5 stop bit"]
773 #[inline]
774 pub fn stop0p5(self) -> &'a mut W {
775 self.variant(STOPW::STOP0P5)
776 }
777 #[doc = "2 stop bit"]
778 #[inline]
779 pub fn stop2(self) -> &'a mut W {
780 self.variant(STOPW::STOP2)
781 }
782 #[doc = "1.5 stop bit"]
783 #[inline]
784 pub fn stop1p5(self) -> &'a mut W {
785 self.variant(STOPW::STOP1P5)
786 }
787 #[doc = r" Writes raw bits to the field"]
788 #[inline]
789 pub fn bits(self, value: u8) -> &'a mut W {
790 const MASK: u8 = 3;
791 const OFFSET: u8 = 12;
792 self.w.bits &= !((MASK as u32) << OFFSET);
793 self.w.bits |= ((value & MASK) as u32) << OFFSET;
794 self.w
795 }
796}
797#[doc = "Values that can be written to the field `CLKEN`"]
798pub enum CLKENW {
799 #[doc = "CK pin disabled"]
800 DISABLED,
801 #[doc = "CK pin enabled"]
802 ENABLED,
803}
804impl CLKENW {
805 #[allow(missing_docs)]
806 #[doc(hidden)]
807 #[inline]
808 pub fn _bits(&self) -> bool {
809 match *self {
810 CLKENW::DISABLED => false,
811 CLKENW::ENABLED => true,
812 }
813 }
814}
815#[doc = r" Proxy"]
816pub struct _CLKENW<'a> {
817 w: &'a mut W,
818}
819impl<'a> _CLKENW<'a> {
820 #[doc = r" Writes `variant` to the field"]
821 #[inline]
822 pub fn variant(self, variant: CLKENW) -> &'a mut W {
823 {
824 self.bit(variant._bits())
825 }
826 }
827 #[doc = "CK pin disabled"]
828 #[inline]
829 pub fn disabled(self) -> &'a mut W {
830 self.variant(CLKENW::DISABLED)
831 }
832 #[doc = "CK pin enabled"]
833 #[inline]
834 pub fn enabled(self) -> &'a mut W {
835 self.variant(CLKENW::ENABLED)
836 }
837 #[doc = r" Sets the field bit"]
838 pub fn set_bit(self) -> &'a mut W {
839 self.bit(true)
840 }
841 #[doc = r" Clears the field bit"]
842 pub fn clear_bit(self) -> &'a mut W {
843 self.bit(false)
844 }
845 #[doc = r" Writes raw bits to the field"]
846 #[inline]
847 pub fn bit(self, value: bool) -> &'a mut W {
848 const MASK: bool = true;
849 const OFFSET: u8 = 11;
850 self.w.bits &= !((MASK as u32) << OFFSET);
851 self.w.bits |= ((value & MASK) as u32) << OFFSET;
852 self.w
853 }
854}
855#[doc = "Values that can be written to the field `ADDM7`"]
856pub enum ADDM7W {
857 #[doc = "4-bit address detection"]
858 BIT4,
859 #[doc = "7-bit address detection"]
860 BIT7,
861}
862impl ADDM7W {
863 #[allow(missing_docs)]
864 #[doc(hidden)]
865 #[inline]
866 pub fn _bits(&self) -> bool {
867 match *self {
868 ADDM7W::BIT4 => false,
869 ADDM7W::BIT7 => true,
870 }
871 }
872}
873#[doc = r" Proxy"]
874pub struct _ADDM7W<'a> {
875 w: &'a mut W,
876}
877impl<'a> _ADDM7W<'a> {
878 #[doc = r" Writes `variant` to the field"]
879 #[inline]
880 pub fn variant(self, variant: ADDM7W) -> &'a mut W {
881 {
882 self.bit(variant._bits())
883 }
884 }
885 #[doc = "4-bit address detection"]
886 #[inline]
887 pub fn bit4(self) -> &'a mut W {
888 self.variant(ADDM7W::BIT4)
889 }
890 #[doc = "7-bit address detection"]
891 #[inline]
892 pub fn bit7(self) -> &'a mut W {
893 self.variant(ADDM7W::BIT7)
894 }
895 #[doc = r" Sets the field bit"]
896 pub fn set_bit(self) -> &'a mut W {
897 self.bit(true)
898 }
899 #[doc = r" Clears the field bit"]
900 pub fn clear_bit(self) -> &'a mut W {
901 self.bit(false)
902 }
903 #[doc = r" Writes raw bits to the field"]
904 #[inline]
905 pub fn bit(self, value: bool) -> &'a mut W {
906 const MASK: bool = true;
907 const OFFSET: u8 = 4;
908 self.w.bits &= !((MASK as u32) << OFFSET);
909 self.w.bits |= ((value & MASK) as u32) << OFFSET;
910 self.w
911 }
912}
913#[doc = r" Proxy"]
914pub struct _ADDW<'a> {
915 w: &'a mut W,
916}
917impl<'a> _ADDW<'a> {
918 #[doc = r" Writes raw bits to the field"]
919 #[inline]
920 pub fn bits(self, value: u8) -> &'a mut W {
921 const MASK: u8 = 255;
922 const OFFSET: u8 = 24;
923 self.w.bits &= !((MASK as u32) << OFFSET);
924 self.w.bits |= ((value & MASK) as u32) << OFFSET;
925 self.w
926 }
927}
928impl R {
929 #[doc = r" Value of the register as raw bits"]
930 #[inline]
931 pub fn bits(&self) -> u32 {
932 self.bits
933 }
934 #[doc = "Bit 19 - Most significant bit first"]
935 #[inline]
936 pub fn msbfirst(&self) -> MSBFIRSTR {
937 MSBFIRSTR::_from({
938 const MASK: bool = true;
939 const OFFSET: u8 = 19;
940 ((self.bits >> OFFSET) & MASK as u32) != 0
941 })
942 }
943 #[doc = "Bit 18 - Binary data inversion"]
944 #[inline]
945 pub fn datainv(&self) -> DATAINVR {
946 DATAINVR::_from({
947 const MASK: bool = true;
948 const OFFSET: u8 = 18;
949 ((self.bits >> OFFSET) & MASK as u32) != 0
950 })
951 }
952 #[doc = "Bit 17 - TX pin active level inversion"]
953 #[inline]
954 pub fn txinv(&self) -> TXINVR {
955 TXINVR::_from({
956 const MASK: bool = true;
957 const OFFSET: u8 = 17;
958 ((self.bits >> OFFSET) & MASK as u32) != 0
959 })
960 }
961 #[doc = "Bit 16 - RX pin active level inversion"]
962 #[inline]
963 pub fn rxinv(&self) -> RXINVR {
964 RXINVR::_from({
965 const MASK: bool = true;
966 const OFFSET: u8 = 16;
967 ((self.bits >> OFFSET) & MASK as u32) != 0
968 })
969 }
970 #[doc = "Bit 15 - Swap TX/RX pins"]
971 #[inline]
972 pub fn swap(&self) -> SWAPR {
973 SWAPR::_from({
974 const MASK: bool = true;
975 const OFFSET: u8 = 15;
976 ((self.bits >> OFFSET) & MASK as u32) != 0
977 })
978 }
979 #[doc = "Bits 12:13 - STOP bits"]
980 #[inline]
981 pub fn stop(&self) -> STOPR {
982 STOPR::_from({
983 const MASK: u8 = 3;
984 const OFFSET: u8 = 12;
985 ((self.bits >> OFFSET) & MASK as u32) as u8
986 })
987 }
988 #[doc = "Bit 11 - Clock enable"]
989 #[inline]
990 pub fn clken(&self) -> CLKENR {
991 CLKENR::_from({
992 const MASK: bool = true;
993 const OFFSET: u8 = 11;
994 ((self.bits >> OFFSET) & MASK as u32) != 0
995 })
996 }
997 #[doc = "Bit 4 - 7-bit Address Detection/4-bit Address Detection"]
998 #[inline]
999 pub fn addm7(&self) -> ADDM7R {
1000 ADDM7R::_from({
1001 const MASK: bool = true;
1002 const OFFSET: u8 = 4;
1003 ((self.bits >> OFFSET) & MASK as u32) != 0
1004 })
1005 }
1006 #[doc = "Bits 24:31 - Address of the USART node"]
1007 #[inline]
1008 pub fn add(&self) -> ADDR {
1009 let bits = {
1010 const MASK: u8 = 255;
1011 const OFFSET: u8 = 24;
1012 ((self.bits >> OFFSET) & MASK as u32) as u8
1013 };
1014 ADDR { bits }
1015 }
1016}
1017impl W {
1018 #[doc = r" Reset value of the register"]
1019 #[inline]
1020 pub fn reset_value() -> W {
1021 W { bits: 0 }
1022 }
1023 #[doc = r" Writes raw bits to the register"]
1024 #[inline]
1025 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1026 self.bits = bits;
1027 self
1028 }
1029 #[doc = "Bit 19 - Most significant bit first"]
1030 #[inline]
1031 pub fn msbfirst(&mut self) -> _MSBFIRSTW {
1032 _MSBFIRSTW { w: self }
1033 }
1034 #[doc = "Bit 18 - Binary data inversion"]
1035 #[inline]
1036 pub fn datainv(&mut self) -> _DATAINVW {
1037 _DATAINVW { w: self }
1038 }
1039 #[doc = "Bit 17 - TX pin active level inversion"]
1040 #[inline]
1041 pub fn txinv(&mut self) -> _TXINVW {
1042 _TXINVW { w: self }
1043 }
1044 #[doc = "Bit 16 - RX pin active level inversion"]
1045 #[inline]
1046 pub fn rxinv(&mut self) -> _RXINVW {
1047 _RXINVW { w: self }
1048 }
1049 #[doc = "Bit 15 - Swap TX/RX pins"]
1050 #[inline]
1051 pub fn swap(&mut self) -> _SWAPW {
1052 _SWAPW { w: self }
1053 }
1054 #[doc = "Bits 12:13 - STOP bits"]
1055 #[inline]
1056 pub fn stop(&mut self) -> _STOPW {
1057 _STOPW { w: self }
1058 }
1059 #[doc = "Bit 11 - Clock enable"]
1060 #[inline]
1061 pub fn clken(&mut self) -> _CLKENW {
1062 _CLKENW { w: self }
1063 }
1064 #[doc = "Bit 4 - 7-bit Address Detection/4-bit Address Detection"]
1065 #[inline]
1066 pub fn addm7(&mut self) -> _ADDM7W {
1067 _ADDM7W { w: self }
1068 }
1069 #[doc = "Bits 24:31 - Address of the USART node"]
1070 #[inline]
1071 pub fn add(&mut self) -> _ADDW {
1072 _ADDW { w: self }
1073 }
1074}