stm32l4x2_pac/lcd/
clr.rs

1#[doc = r" Value to write to the register"]
2pub struct W {
3    bits: u32,
4}
5impl super::CLR {
6    #[doc = r" Writes to the register"]
7    #[inline]
8    pub fn write<F>(&self, f: F)
9    where
10        F: FnOnce(&mut W) -> &mut W,
11    {
12        let mut w = W::reset_value();
13        f(&mut w);
14        self.register.set(w.bits);
15    }
16}
17#[doc = r" Proxy"]
18pub struct _UDDCW<'a> {
19    w: &'a mut W,
20}
21impl<'a> _UDDCW<'a> {
22    #[doc = r" Sets the field bit"]
23    pub fn set_bit(self) -> &'a mut W {
24        self.bit(true)
25    }
26    #[doc = r" Clears the field bit"]
27    pub fn clear_bit(self) -> &'a mut W {
28        self.bit(false)
29    }
30    #[doc = r" Writes raw bits to the field"]
31    #[inline]
32    pub fn bit(self, value: bool) -> &'a mut W {
33        const MASK: bool = true;
34        const OFFSET: u8 = 3;
35        self.w.bits &= !((MASK as u32) << OFFSET);
36        self.w.bits |= ((value & MASK) as u32) << OFFSET;
37        self.w
38    }
39}
40#[doc = r" Proxy"]
41pub struct _SOFCW<'a> {
42    w: &'a mut W,
43}
44impl<'a> _SOFCW<'a> {
45    #[doc = r" Sets the field bit"]
46    pub fn set_bit(self) -> &'a mut W {
47        self.bit(true)
48    }
49    #[doc = r" Clears the field bit"]
50    pub fn clear_bit(self) -> &'a mut W {
51        self.bit(false)
52    }
53    #[doc = r" Writes raw bits to the field"]
54    #[inline]
55    pub fn bit(self, value: bool) -> &'a mut W {
56        const MASK: bool = true;
57        const OFFSET: u8 = 1;
58        self.w.bits &= !((MASK as u32) << OFFSET);
59        self.w.bits |= ((value & MASK) as u32) << OFFSET;
60        self.w
61    }
62}
63impl W {
64    #[doc = r" Reset value of the register"]
65    #[inline]
66    pub fn reset_value() -> W {
67        W { bits: 0 }
68    }
69    #[doc = r" Writes raw bits to the register"]
70    #[inline]
71    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
72        self.bits = bits;
73        self
74    }
75    #[doc = "Bit 3 - Update display done clear"]
76    #[inline]
77    pub fn uddc(&mut self) -> _UDDCW {
78        _UDDCW { w: self }
79    }
80    #[doc = "Bit 1 - Start of frame flag clear"]
81    #[inline]
82    pub fn sofc(&mut self) -> _SOFCW {
83        _SOFCW { w: self }
84    }
85}
stm32l4x2_pac/lcd/clr.rs

stm32l4x2_pac/lcd/
clr.rs
