stm32l4x2_pac/iwdg/
sr.rs

1#[doc = r" Value read from the register"]
2pub struct R {
3    bits: u32,
4}
5impl super::SR {
6    #[doc = r" Reads the contents of the register"]
7    #[inline]
8    pub fn read(&self) -> R {
9        R {
10            bits: self.register.get(),
11        }
12    }
13}
14#[doc = r" Value of the field"]
15pub struct WVUR {
16    bits: bool,
17}
18impl WVUR {
19    #[doc = r" Value of the field as raw bits"]
20    #[inline]
21    pub fn bit(&self) -> bool {
22        self.bits
23    }
24    #[doc = r" Returns `true` if the bit is clear (0)"]
25    #[inline]
26    pub fn bit_is_clear(&self) -> bool {
27        !self.bit()
28    }
29    #[doc = r" Returns `true` if the bit is set (1)"]
30    #[inline]
31    pub fn bit_is_set(&self) -> bool {
32        self.bit()
33    }
34}
35#[doc = r" Value of the field"]
36pub struct RVUR {
37    bits: bool,
38}
39impl RVUR {
40    #[doc = r" Value of the field as raw bits"]
41    #[inline]
42    pub fn bit(&self) -> bool {
43        self.bits
44    }
45    #[doc = r" Returns `true` if the bit is clear (0)"]
46    #[inline]
47    pub fn bit_is_clear(&self) -> bool {
48        !self.bit()
49    }
50    #[doc = r" Returns `true` if the bit is set (1)"]
51    #[inline]
52    pub fn bit_is_set(&self) -> bool {
53        self.bit()
54    }
55}
56#[doc = r" Value of the field"]
57pub struct PVUR {
58    bits: bool,
59}
60impl PVUR {
61    #[doc = r" Value of the field as raw bits"]
62    #[inline]
63    pub fn bit(&self) -> bool {
64        self.bits
65    }
66    #[doc = r" Returns `true` if the bit is clear (0)"]
67    #[inline]
68    pub fn bit_is_clear(&self) -> bool {
69        !self.bit()
70    }
71    #[doc = r" Returns `true` if the bit is set (1)"]
72    #[inline]
73    pub fn bit_is_set(&self) -> bool {
74        self.bit()
75    }
76}
77impl R {
78    #[doc = r" Value of the register as raw bits"]
79    #[inline]
80    pub fn bits(&self) -> u32 {
81        self.bits
82    }
83    #[doc = "Bit 2 - Watchdog counter window value update"]
84    #[inline]
85    pub fn wvu(&self) -> WVUR {
86        let bits = {
87            const MASK: bool = true;
88            const OFFSET: u8 = 2;
89            ((self.bits >> OFFSET) & MASK as u32) != 0
90        };
91        WVUR { bits }
92    }
93    #[doc = "Bit 1 - Watchdog counter reload value update"]
94    #[inline]
95    pub fn rvu(&self) -> RVUR {
96        let bits = {
97            const MASK: bool = true;
98            const OFFSET: u8 = 1;
99            ((self.bits >> OFFSET) & MASK as u32) != 0
100        };
101        RVUR { bits }
102    }
103    #[doc = "Bit 0 - Watchdog prescaler value update"]
104    #[inline]
105    pub fn pvu(&self) -> PVUR {
106        let bits = {
107            const MASK: bool = true;
108            const OFFSET: u8 = 0;
109            ((self.bits >> OFFSET) & MASK as u32) != 0
110        };
111        PVUR { bits }
112    }
113}
stm32l4x2_pac/iwdg/sr.rs

stm32l4x2_pac/iwdg/
sr.rs
