1#[doc = r" Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "0x00 - control register"]
5 pub cr: CR,
6 #[doc = "0x04 - software trigger register"]
7 pub swtrigr: SWTRIGR,
8 #[doc = "0x08 - channel1 12-bit right-aligned data holding register"]
9 pub dhr12r1: DHR12R1,
10 #[doc = "0x0c - channel1 12-bit left-aligned data holding register"]
11 pub dhr12l1: DHR12L1,
12 #[doc = "0x10 - channel1 8-bit right-aligned data holding register"]
13 pub dhr8r1: DHR8R1,
14 #[doc = "0x14 - channel2 12-bit right aligned data holding register"]
15 pub dhr12r2: DHR12R2,
16 #[doc = "0x18 - channel2 12-bit left aligned data holding register"]
17 pub dhr12l2: DHR12L2,
18 #[doc = "0x1c - channel2 8-bit right-aligned data holding register"]
19 pub dhr8r2: DHR8R2,
20 #[doc = "0x20 - Dual DAC 12-bit right-aligned data holding register"]
21 pub dhr12rd: DHR12RD,
22 #[doc = "0x24 - DUAL DAC 12-bit left aligned data holding register"]
23 pub dhr12ld: DHR12LD,
24 #[doc = "0x28 - DUAL DAC 8-bit right aligned data holding register"]
25 pub dhr8rd: DHR8RD,
26 #[doc = "0x2c - channel1 data output register"]
27 pub dor1: DOR1,
28 #[doc = "0x30 - channel2 data output register"]
29 pub dor2: DOR2,
30 #[doc = "0x34 - status register"]
31 pub sr: SR,
32 #[doc = "0x38 - calibration control register"]
33 pub ccr: CCR,
34 #[doc = "0x3c - mode control register"]
35 pub mcr: MCR,
36 #[doc = "0x40 - Sample and Hold sample time register 1"]
37 pub shsr1: SHSR1,
38 #[doc = "0x44 - Sample and Hold sample time register 2"]
39 pub shsr2: SHSR2,
40 #[doc = "0x48 - Sample and Hold hold time register"]
41 pub shhr: SHHR,
42 #[doc = "0x4c - Sample and Hold refresh time register"]
43 pub shrr: SHRR,
44}
45#[doc = "control register"]
46pub struct CR {
47 register: ::vcell::VolatileCell<u32>,
48}
49#[doc = "control register"]
50pub mod cr;
51#[doc = "software trigger register"]
52pub struct SWTRIGR {
53 register: ::vcell::VolatileCell<u32>,
54}
55#[doc = "software trigger register"]
56pub mod swtrigr;
57#[doc = "channel1 12-bit right-aligned data holding register"]
58pub struct DHR12R1 {
59 register: ::vcell::VolatileCell<u32>,
60}
61#[doc = "channel1 12-bit right-aligned data holding register"]
62pub mod dhr12r1;
63#[doc = "channel1 12-bit left-aligned data holding register"]
64pub struct DHR12L1 {
65 register: ::vcell::VolatileCell<u32>,
66}
67#[doc = "channel1 12-bit left-aligned data holding register"]
68pub mod dhr12l1;
69#[doc = "channel1 8-bit right-aligned data holding register"]
70pub struct DHR8R1 {
71 register: ::vcell::VolatileCell<u32>,
72}
73#[doc = "channel1 8-bit right-aligned data holding register"]
74pub mod dhr8r1;
75#[doc = "channel2 12-bit right aligned data holding register"]
76pub struct DHR12R2 {
77 register: ::vcell::VolatileCell<u32>,
78}
79#[doc = "channel2 12-bit right aligned data holding register"]
80pub mod dhr12r2;
81#[doc = "channel2 12-bit left aligned data holding register"]
82pub struct DHR12L2 {
83 register: ::vcell::VolatileCell<u32>,
84}
85#[doc = "channel2 12-bit left aligned data holding register"]
86pub mod dhr12l2;
87#[doc = "channel2 8-bit right-aligned data holding register"]
88pub struct DHR8R2 {
89 register: ::vcell::VolatileCell<u32>,
90}
91#[doc = "channel2 8-bit right-aligned data holding register"]
92pub mod dhr8r2;
93#[doc = "Dual DAC 12-bit right-aligned data holding register"]
94pub struct DHR12RD {
95 register: ::vcell::VolatileCell<u32>,
96}
97#[doc = "Dual DAC 12-bit right-aligned data holding register"]
98pub mod dhr12rd;
99#[doc = "DUAL DAC 12-bit left aligned data holding register"]
100pub struct DHR12LD {
101 register: ::vcell::VolatileCell<u32>,
102}
103#[doc = "DUAL DAC 12-bit left aligned data holding register"]
104pub mod dhr12ld;
105#[doc = "DUAL DAC 8-bit right aligned data holding register"]
106pub struct DHR8RD {
107 register: ::vcell::VolatileCell<u32>,
108}
109#[doc = "DUAL DAC 8-bit right aligned data holding register"]
110pub mod dhr8rd;
111#[doc = "channel1 data output register"]
112pub struct DOR1 {
113 register: ::vcell::VolatileCell<u32>,
114}
115#[doc = "channel1 data output register"]
116pub mod dor1;
117#[doc = "channel2 data output register"]
118pub struct DOR2 {
119 register: ::vcell::VolatileCell<u32>,
120}
121#[doc = "channel2 data output register"]
122pub mod dor2;
123#[doc = "status register"]
124pub struct SR {
125 register: ::vcell::VolatileCell<u32>,
126}
127#[doc = "status register"]
128pub mod sr;
129#[doc = "calibration control register"]
130pub struct CCR {
131 register: ::vcell::VolatileCell<u32>,
132}
133#[doc = "calibration control register"]
134pub mod ccr;
135#[doc = "mode control register"]
136pub struct MCR {
137 register: ::vcell::VolatileCell<u32>,
138}
139#[doc = "mode control register"]
140pub mod mcr;
141#[doc = "Sample and Hold sample time register 1"]
142pub struct SHSR1 {
143 register: ::vcell::VolatileCell<u32>,
144}
145#[doc = "Sample and Hold sample time register 1"]
146pub mod shsr1;
147#[doc = "Sample and Hold sample time register 2"]
148pub struct SHSR2 {
149 register: ::vcell::VolatileCell<u32>,
150}
151#[doc = "Sample and Hold sample time register 2"]
152pub mod shsr2;
153#[doc = "Sample and Hold hold time register"]
154pub struct SHHR {
155 register: ::vcell::VolatileCell<u32>,
156}
157#[doc = "Sample and Hold hold time register"]
158pub mod shhr;
159#[doc = "Sample and Hold refresh time register"]
160pub struct SHRR {
161 register: ::vcell::VolatileCell<u32>,
162}
163#[doc = "Sample and Hold refresh time register"]
164pub mod shrr;