stm32l4x2_pac/can1/rx/
rdlr.rs1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5impl super::RDLR {
6 #[doc = r" Reads the contents of the register"]
7 #[inline]
8 pub fn read(&self) -> R {
9 R {
10 bits: self.register.get(),
11 }
12 }
13}
14#[doc = r" Value of the field"]
15pub struct DATA3R {
16 bits: u8,
17}
18impl DATA3R {
19 #[doc = r" Value of the field as raw bits"]
20 #[inline]
21 pub fn bits(&self) -> u8 {
22 self.bits
23 }
24}
25#[doc = r" Value of the field"]
26pub struct DATA2R {
27 bits: u8,
28}
29impl DATA2R {
30 #[doc = r" Value of the field as raw bits"]
31 #[inline]
32 pub fn bits(&self) -> u8 {
33 self.bits
34 }
35}
36#[doc = r" Value of the field"]
37pub struct DATA1R {
38 bits: u8,
39}
40impl DATA1R {
41 #[doc = r" Value of the field as raw bits"]
42 #[inline]
43 pub fn bits(&self) -> u8 {
44 self.bits
45 }
46}
47#[doc = r" Value of the field"]
48pub struct DATA0R {
49 bits: u8,
50}
51impl DATA0R {
52 #[doc = r" Value of the field as raw bits"]
53 #[inline]
54 pub fn bits(&self) -> u8 {
55 self.bits
56 }
57}
58impl R {
59 #[doc = r" Value of the register as raw bits"]
60 #[inline]
61 pub fn bits(&self) -> u32 {
62 self.bits
63 }
64 #[doc = "Bits 24:31 - DATA3"]
65 #[inline]
66 pub fn data3(&self) -> DATA3R {
67 let bits = {
68 const MASK: u8 = 255;
69 const OFFSET: u8 = 24;
70 ((self.bits >> OFFSET) & MASK as u32) as u8
71 };
72 DATA3R { bits }
73 }
74 #[doc = "Bits 16:23 - DATA2"]
75 #[inline]
76 pub fn data2(&self) -> DATA2R {
77 let bits = {
78 const MASK: u8 = 255;
79 const OFFSET: u8 = 16;
80 ((self.bits >> OFFSET) & MASK as u32) as u8
81 };
82 DATA2R { bits }
83 }
84 #[doc = "Bits 8:15 - DATA1"]
85 #[inline]
86 pub fn data1(&self) -> DATA1R {
87 let bits = {
88 const MASK: u8 = 255;
89 const OFFSET: u8 = 8;
90 ((self.bits >> OFFSET) & MASK as u32) as u8
91 };
92 DATA1R { bits }
93 }
94 #[doc = "Bits 0:7 - DATA0"]
95 #[inline]
96 pub fn data0(&self) -> DATA0R {
97 let bits = {
98 const MASK: u8 = 255;
99 const OFFSET: u8 = 0;
100 ((self.bits >> OFFSET) & MASK as u32) as u8
101 };
102 DATA0R { bits }
103 }
104}