stm32l4x2_pac/tim6/
cr2.rs

1#[doc = r" Value read from the register"]
2pub struct R {
3    bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7    bits: u32,
8}
9impl super::CR2 {
10    #[doc = r" Modifies the contents of the register"]
11    #[inline]
12    pub fn modify<F>(&self, f: F)
13    where
14        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15    {
16        let bits = self.register.get();
17        let r = R { bits: bits };
18        let mut w = W { bits: bits };
19        f(&r, &mut w);
20        self.register.set(w.bits);
21    }
22    #[doc = r" Reads the contents of the register"]
23    #[inline]
24    pub fn read(&self) -> R {
25        R {
26            bits: self.register.get(),
27        }
28    }
29    #[doc = r" Writes to the register"]
30    #[inline]
31    pub fn write<F>(&self, f: F)
32    where
33        F: FnOnce(&mut W) -> &mut W,
34    {
35        let mut w = W::reset_value();
36        f(&mut w);
37        self.register.set(w.bits);
38    }
39    #[doc = r" Writes the reset value to the register"]
40    #[inline]
41    pub fn reset(&self) {
42        self.write(|w| w)
43    }
44}
45#[doc = "Possible values of the field `MMS`"]
46#[derive(Clone, Copy, Debug, PartialEq)]
47pub enum MMSR {
48    #[doc = "Use UG bit from TIMx_EGR register"]
49    RESET,
50    #[doc = "Use CNT bit from TIMx_CEN register"]
51    ENABLE,
52    #[doc = "Use the update event"]
53    UPDATE,
54    #[doc = r" Reserved"]
55    _Reserved(u8),
56}
57impl MMSR {
58    #[doc = r" Value of the field as raw bits"]
59    #[inline]
60    pub fn bits(&self) -> u8 {
61        match *self {
62            MMSR::RESET => 0,
63            MMSR::ENABLE => 1,
64            MMSR::UPDATE => 2,
65            MMSR::_Reserved(bits) => bits,
66        }
67    }
68    #[allow(missing_docs)]
69    #[doc(hidden)]
70    #[inline]
71    pub fn _from(value: u8) -> MMSR {
72        match value {
73            0 => MMSR::RESET,
74            1 => MMSR::ENABLE,
75            2 => MMSR::UPDATE,
76            i => MMSR::_Reserved(i),
77        }
78    }
79    #[doc = "Checks if the value of the field is `RESET`"]
80    #[inline]
81    pub fn is_reset(&self) -> bool {
82        *self == MMSR::RESET
83    }
84    #[doc = "Checks if the value of the field is `ENABLE`"]
85    #[inline]
86    pub fn is_enable(&self) -> bool {
87        *self == MMSR::ENABLE
88    }
89    #[doc = "Checks if the value of the field is `UPDATE`"]
90    #[inline]
91    pub fn is_update(&self) -> bool {
92        *self == MMSR::UPDATE
93    }
94}
95#[doc = "Values that can be written to the field `MMS`"]
96pub enum MMSW {
97    #[doc = "Use UG bit from TIMx_EGR register"]
98    RESET,
99    #[doc = "Use CNT bit from TIMx_CEN register"]
100    ENABLE,
101    #[doc = "Use the update event"]
102    UPDATE,
103}
104impl MMSW {
105    #[allow(missing_docs)]
106    #[doc(hidden)]
107    #[inline]
108    pub fn _bits(&self) -> u8 {
109        match *self {
110            MMSW::RESET => 0,
111            MMSW::ENABLE => 1,
112            MMSW::UPDATE => 2,
113        }
114    }
115}
116#[doc = r" Proxy"]
117pub struct _MMSW<'a> {
118    w: &'a mut W,
119}
120impl<'a> _MMSW<'a> {
121    #[doc = r" Writes `variant` to the field"]
122    #[inline]
123    pub fn variant(self, variant: MMSW) -> &'a mut W {
124        unsafe { self.bits(variant._bits()) }
125    }
126    #[doc = "Use UG bit from TIMx_EGR register"]
127    #[inline]
128    pub fn reset(self) -> &'a mut W {
129        self.variant(MMSW::RESET)
130    }
131    #[doc = "Use CNT bit from TIMx_CEN register"]
132    #[inline]
133    pub fn enable(self) -> &'a mut W {
134        self.variant(MMSW::ENABLE)
135    }
136    #[doc = "Use the update event"]
137    #[inline]
138    pub fn update(self) -> &'a mut W {
139        self.variant(MMSW::UPDATE)
140    }
141    #[doc = r" Writes raw bits to the field"]
142    #[inline]
143    pub unsafe fn bits(self, value: u8) -> &'a mut W {
144        const MASK: u8 = 7;
145        const OFFSET: u8 = 4;
146        self.w.bits &= !((MASK as u32) << OFFSET);
147        self.w.bits |= ((value & MASK) as u32) << OFFSET;
148        self.w
149    }
150}
151impl R {
152    #[doc = r" Value of the register as raw bits"]
153    #[inline]
154    pub fn bits(&self) -> u32 {
155        self.bits
156    }
157    #[doc = "Bits 4:6 - Master mode selection"]
158    #[inline]
159    pub fn mms(&self) -> MMSR {
160        MMSR::_from({
161            const MASK: u8 = 7;
162            const OFFSET: u8 = 4;
163            ((self.bits >> OFFSET) & MASK as u32) as u8
164        })
165    }
166}
167impl W {
168    #[doc = r" Reset value of the register"]
169    #[inline]
170    pub fn reset_value() -> W {
171        W { bits: 0 }
172    }
173    #[doc = r" Writes raw bits to the register"]
174    #[inline]
175    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
176        self.bits = bits;
177        self
178    }
179    #[doc = "Bits 4:6 - Master mode selection"]
180    #[inline]
181    pub fn mms(&mut self) -> _MMSW {
182        _MMSW { w: self }
183    }
184}
stm32l4x2_pac/tim6/cr2.rs

stm32l4x2_pac/tim6/
cr2.rs
