1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::SMCR {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = "Possible values of the field `ETP`"]
46#[derive(Clone, Copy, Debug, PartialEq)]
47pub enum ETPR {
48 #[doc = "ETR is noninverted, active at high level or rising edge"]
49 NOTINVERTED,
50 #[doc = "ETR is inverted, active at low level or falling edge"]
51 INVERTED,
52}
53impl ETPR {
54 #[doc = r" Returns `true` if the bit is clear (0)"]
55 #[inline]
56 pub fn bit_is_clear(&self) -> bool {
57 !self.bit()
58 }
59 #[doc = r" Returns `true` if the bit is set (1)"]
60 #[inline]
61 pub fn bit_is_set(&self) -> bool {
62 self.bit()
63 }
64 #[doc = r" Value of the field as raw bits"]
65 #[inline]
66 pub fn bit(&self) -> bool {
67 match *self {
68 ETPR::NOTINVERTED => false,
69 ETPR::INVERTED => true,
70 }
71 }
72 #[allow(missing_docs)]
73 #[doc(hidden)]
74 #[inline]
75 pub fn _from(value: bool) -> ETPR {
76 match value {
77 false => ETPR::NOTINVERTED,
78 true => ETPR::INVERTED,
79 }
80 }
81 #[doc = "Checks if the value of the field is `NOTINVERTED`"]
82 #[inline]
83 pub fn is_not_inverted(&self) -> bool {
84 *self == ETPR::NOTINVERTED
85 }
86 #[doc = "Checks if the value of the field is `INVERTED`"]
87 #[inline]
88 pub fn is_inverted(&self) -> bool {
89 *self == ETPR::INVERTED
90 }
91}
92#[doc = "Possible values of the field `ECE`"]
93#[derive(Clone, Copy, Debug, PartialEq)]
94pub enum ECER {
95 #[doc = "External clock mode 2 disabled"]
96 DISABLED,
97 #[doc = "External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal."]
98 ENABLED,
99}
100impl ECER {
101 #[doc = r" Returns `true` if the bit is clear (0)"]
102 #[inline]
103 pub fn bit_is_clear(&self) -> bool {
104 !self.bit()
105 }
106 #[doc = r" Returns `true` if the bit is set (1)"]
107 #[inline]
108 pub fn bit_is_set(&self) -> bool {
109 self.bit()
110 }
111 #[doc = r" Value of the field as raw bits"]
112 #[inline]
113 pub fn bit(&self) -> bool {
114 match *self {
115 ECER::DISABLED => false,
116 ECER::ENABLED => true,
117 }
118 }
119 #[allow(missing_docs)]
120 #[doc(hidden)]
121 #[inline]
122 pub fn _from(value: bool) -> ECER {
123 match value {
124 false => ECER::DISABLED,
125 true => ECER::ENABLED,
126 }
127 }
128 #[doc = "Checks if the value of the field is `DISABLED`"]
129 #[inline]
130 pub fn is_disabled(&self) -> bool {
131 *self == ECER::DISABLED
132 }
133 #[doc = "Checks if the value of the field is `ENABLED`"]
134 #[inline]
135 pub fn is_enabled(&self) -> bool {
136 *self == ECER::ENABLED
137 }
138}
139#[doc = "Possible values of the field `ETPS`"]
140#[derive(Clone, Copy, Debug, PartialEq)]
141pub enum ETPSR {
142 #[doc = "Prescaler OFF"]
143 NODIV,
144 #[doc = "ETRP frequency divided by 2"]
145 DIV2,
146 #[doc = "ETRP frequency divided by 4"]
147 DIV4,
148 #[doc = "ETRP frequency divided by 8"]
149 DIV8,
150}
151impl ETPSR {
152 #[doc = r" Value of the field as raw bits"]
153 #[inline]
154 pub fn bits(&self) -> u8 {
155 match *self {
156 ETPSR::NODIV => 0,
157 ETPSR::DIV2 => 1,
158 ETPSR::DIV4 => 2,
159 ETPSR::DIV8 => 3,
160 }
161 }
162 #[allow(missing_docs)]
163 #[doc(hidden)]
164 #[inline]
165 pub fn _from(value: u8) -> ETPSR {
166 match value {
167 0 => ETPSR::NODIV,
168 1 => ETPSR::DIV2,
169 2 => ETPSR::DIV4,
170 3 => ETPSR::DIV8,
171 _ => unreachable!(),
172 }
173 }
174 #[doc = "Checks if the value of the field is `NODIV`"]
175 #[inline]
176 pub fn is_no_div(&self) -> bool {
177 *self == ETPSR::NODIV
178 }
179 #[doc = "Checks if the value of the field is `DIV2`"]
180 #[inline]
181 pub fn is_div2(&self) -> bool {
182 *self == ETPSR::DIV2
183 }
184 #[doc = "Checks if the value of the field is `DIV4`"]
185 #[inline]
186 pub fn is_div4(&self) -> bool {
187 *self == ETPSR::DIV4
188 }
189 #[doc = "Checks if the value of the field is `DIV8`"]
190 #[inline]
191 pub fn is_div8(&self) -> bool {
192 *self == ETPSR::DIV8
193 }
194}
195#[doc = "Possible values of the field `ETF`"]
196#[derive(Clone, Copy, Debug, PartialEq)]
197pub enum ETFR {
198 #[doc = "No filter, sampling is done at fDTS"]
199 NOFILTER,
200 #[doc = "fSAMPLING=fCK_INT, N=2"]
201 FCK_INT_N2,
202 #[doc = "fSAMPLING=fCK_INT, N=4"]
203 FCK_INT_N4,
204 #[doc = "fSAMPLING=fCK_INT, N=8"]
205 FCK_INT_N8,
206 #[doc = "fSAMPLING=fDTS/2, N=6"]
207 FDTS_DIV2_N6,
208 #[doc = "fSAMPLING=fDTS/2, N=8"]
209 FDTS_DIV2_N8,
210 #[doc = "fSAMPLING=fDTS/4, N=6"]
211 FDTS_DIV4_N6,
212 #[doc = "fSAMPLING=fDTS/4, N=8"]
213 FDTS_DIV4_N8,
214 #[doc = "fSAMPLING=fDTS/8, N=6"]
215 FDTS_DIV8_N6,
216 #[doc = "fSAMPLING=fDTS/8, N=8"]
217 FDTS_DIV8_N8,
218 #[doc = "fSAMPLING=fDTS/16, N=5"]
219 FDTS_DIV16_N5,
220 #[doc = "fSAMPLING=fDTS/16, N=6"]
221 FDTS_DIV16_N6,
222 #[doc = "fSAMPLING=fDTS/16, N=8"]
223 FDTS_DIV16_N8,
224 #[doc = "fSAMPLING=fDTS/32, N=5"]
225 FDTS_DIV32_N5,
226 #[doc = "fSAMPLING=fDTS/32, N=6"]
227 FDTS_DIV32_N6,
228 #[doc = "fSAMPLING=fDTS/32, N=8"]
229 FDTS_DIV32_N8,
230}
231impl ETFR {
232 #[doc = r" Value of the field as raw bits"]
233 #[inline]
234 pub fn bits(&self) -> u8 {
235 match *self {
236 ETFR::NOFILTER => 0,
237 ETFR::FCK_INT_N2 => 1,
238 ETFR::FCK_INT_N4 => 2,
239 ETFR::FCK_INT_N8 => 3,
240 ETFR::FDTS_DIV2_N6 => 4,
241 ETFR::FDTS_DIV2_N8 => 5,
242 ETFR::FDTS_DIV4_N6 => 6,
243 ETFR::FDTS_DIV4_N8 => 7,
244 ETFR::FDTS_DIV8_N6 => 8,
245 ETFR::FDTS_DIV8_N8 => 9,
246 ETFR::FDTS_DIV16_N5 => 10,
247 ETFR::FDTS_DIV16_N6 => 11,
248 ETFR::FDTS_DIV16_N8 => 12,
249 ETFR::FDTS_DIV32_N5 => 13,
250 ETFR::FDTS_DIV32_N6 => 14,
251 ETFR::FDTS_DIV32_N8 => 15,
252 }
253 }
254 #[allow(missing_docs)]
255 #[doc(hidden)]
256 #[inline]
257 pub fn _from(value: u8) -> ETFR {
258 match value {
259 0 => ETFR::NOFILTER,
260 1 => ETFR::FCK_INT_N2,
261 2 => ETFR::FCK_INT_N4,
262 3 => ETFR::FCK_INT_N8,
263 4 => ETFR::FDTS_DIV2_N6,
264 5 => ETFR::FDTS_DIV2_N8,
265 6 => ETFR::FDTS_DIV4_N6,
266 7 => ETFR::FDTS_DIV4_N8,
267 8 => ETFR::FDTS_DIV8_N6,
268 9 => ETFR::FDTS_DIV8_N8,
269 10 => ETFR::FDTS_DIV16_N5,
270 11 => ETFR::FDTS_DIV16_N6,
271 12 => ETFR::FDTS_DIV16_N8,
272 13 => ETFR::FDTS_DIV32_N5,
273 14 => ETFR::FDTS_DIV32_N6,
274 15 => ETFR::FDTS_DIV32_N8,
275 _ => unreachable!(),
276 }
277 }
278 #[doc = "Checks if the value of the field is `NOFILTER`"]
279 #[inline]
280 pub fn is_no_filter(&self) -> bool {
281 *self == ETFR::NOFILTER
282 }
283 #[doc = "Checks if the value of the field is `FCK_INT_N2`"]
284 #[inline]
285 pub fn is_fck_int_n2(&self) -> bool {
286 *self == ETFR::FCK_INT_N2
287 }
288 #[doc = "Checks if the value of the field is `FCK_INT_N4`"]
289 #[inline]
290 pub fn is_fck_int_n4(&self) -> bool {
291 *self == ETFR::FCK_INT_N4
292 }
293 #[doc = "Checks if the value of the field is `FCK_INT_N8`"]
294 #[inline]
295 pub fn is_fck_int_n8(&self) -> bool {
296 *self == ETFR::FCK_INT_N8
297 }
298 #[doc = "Checks if the value of the field is `FDTS_DIV2_N6`"]
299 #[inline]
300 pub fn is_fdts_div2_n6(&self) -> bool {
301 *self == ETFR::FDTS_DIV2_N6
302 }
303 #[doc = "Checks if the value of the field is `FDTS_DIV2_N8`"]
304 #[inline]
305 pub fn is_fdts_div2_n8(&self) -> bool {
306 *self == ETFR::FDTS_DIV2_N8
307 }
308 #[doc = "Checks if the value of the field is `FDTS_DIV4_N6`"]
309 #[inline]
310 pub fn is_fdts_div4_n6(&self) -> bool {
311 *self == ETFR::FDTS_DIV4_N6
312 }
313 #[doc = "Checks if the value of the field is `FDTS_DIV4_N8`"]
314 #[inline]
315 pub fn is_fdts_div4_n8(&self) -> bool {
316 *self == ETFR::FDTS_DIV4_N8
317 }
318 #[doc = "Checks if the value of the field is `FDTS_DIV8_N6`"]
319 #[inline]
320 pub fn is_fdts_div8_n6(&self) -> bool {
321 *self == ETFR::FDTS_DIV8_N6
322 }
323 #[doc = "Checks if the value of the field is `FDTS_DIV8_N8`"]
324 #[inline]
325 pub fn is_fdts_div8_n8(&self) -> bool {
326 *self == ETFR::FDTS_DIV8_N8
327 }
328 #[doc = "Checks if the value of the field is `FDTS_DIV16_N5`"]
329 #[inline]
330 pub fn is_fdts_div16_n5(&self) -> bool {
331 *self == ETFR::FDTS_DIV16_N5
332 }
333 #[doc = "Checks if the value of the field is `FDTS_DIV16_N6`"]
334 #[inline]
335 pub fn is_fdts_div16_n6(&self) -> bool {
336 *self == ETFR::FDTS_DIV16_N6
337 }
338 #[doc = "Checks if the value of the field is `FDTS_DIV16_N8`"]
339 #[inline]
340 pub fn is_fdts_div16_n8(&self) -> bool {
341 *self == ETFR::FDTS_DIV16_N8
342 }
343 #[doc = "Checks if the value of the field is `FDTS_DIV32_N5`"]
344 #[inline]
345 pub fn is_fdts_div32_n5(&self) -> bool {
346 *self == ETFR::FDTS_DIV32_N5
347 }
348 #[doc = "Checks if the value of the field is `FDTS_DIV32_N6`"]
349 #[inline]
350 pub fn is_fdts_div32_n6(&self) -> bool {
351 *self == ETFR::FDTS_DIV32_N6
352 }
353 #[doc = "Checks if the value of the field is `FDTS_DIV32_N8`"]
354 #[inline]
355 pub fn is_fdts_div32_n8(&self) -> bool {
356 *self == ETFR::FDTS_DIV32_N8
357 }
358}
359#[doc = "Possible values of the field `MSM`"]
360#[derive(Clone, Copy, Debug, PartialEq)]
361pub enum MSMR {
362 #[doc = "No action"]
363 NOSYNC,
364 #[doc = "The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."]
365 SYNC,
366}
367impl MSMR {
368 #[doc = r" Returns `true` if the bit is clear (0)"]
369 #[inline]
370 pub fn bit_is_clear(&self) -> bool {
371 !self.bit()
372 }
373 #[doc = r" Returns `true` if the bit is set (1)"]
374 #[inline]
375 pub fn bit_is_set(&self) -> bool {
376 self.bit()
377 }
378 #[doc = r" Value of the field as raw bits"]
379 #[inline]
380 pub fn bit(&self) -> bool {
381 match *self {
382 MSMR::NOSYNC => false,
383 MSMR::SYNC => true,
384 }
385 }
386 #[allow(missing_docs)]
387 #[doc(hidden)]
388 #[inline]
389 pub fn _from(value: bool) -> MSMR {
390 match value {
391 false => MSMR::NOSYNC,
392 true => MSMR::SYNC,
393 }
394 }
395 #[doc = "Checks if the value of the field is `NOSYNC`"]
396 #[inline]
397 pub fn is_no_sync(&self) -> bool {
398 *self == MSMR::NOSYNC
399 }
400 #[doc = "Checks if the value of the field is `SYNC`"]
401 #[inline]
402 pub fn is_sync(&self) -> bool {
403 *self == MSMR::SYNC
404 }
405}
406#[doc = "Possible values of the field `TS`"]
407#[derive(Clone, Copy, Debug, PartialEq)]
408pub enum TSR {
409 #[doc = "Internal Trigger 0 (ITR0)"]
410 ITR0,
411 #[doc = "Internal Trigger 1 (ITR1)"]
412 ITR1,
413 #[doc = "Internal Trigger 2 (ITR2)"]
414 ITR2,
415 #[doc = "TI1 Edge Detector (TI1F_ED)"]
416 TI1F_ED,
417 #[doc = "Filtered Timer Input 1 (TI1FP1)"]
418 TI1FP1,
419 #[doc = "Filtered Timer Input 2 (TI2FP2)"]
420 TI2FP2,
421 #[doc = "External Trigger input (ETRF)"]
422 ETRF,
423 #[doc = r" Reserved"]
424 _Reserved(u8),
425}
426impl TSR {
427 #[doc = r" Value of the field as raw bits"]
428 #[inline]
429 pub fn bits(&self) -> u8 {
430 match *self {
431 TSR::ITR0 => 0,
432 TSR::ITR1 => 1,
433 TSR::ITR2 => 2,
434 TSR::TI1F_ED => 4,
435 TSR::TI1FP1 => 5,
436 TSR::TI2FP2 => 6,
437 TSR::ETRF => 7,
438 TSR::_Reserved(bits) => bits,
439 }
440 }
441 #[allow(missing_docs)]
442 #[doc(hidden)]
443 #[inline]
444 pub fn _from(value: u8) -> TSR {
445 match value {
446 0 => TSR::ITR0,
447 1 => TSR::ITR1,
448 2 => TSR::ITR2,
449 4 => TSR::TI1F_ED,
450 5 => TSR::TI1FP1,
451 6 => TSR::TI2FP2,
452 7 => TSR::ETRF,
453 i => TSR::_Reserved(i),
454 }
455 }
456 #[doc = "Checks if the value of the field is `ITR0`"]
457 #[inline]
458 pub fn is_itr0(&self) -> bool {
459 *self == TSR::ITR0
460 }
461 #[doc = "Checks if the value of the field is `ITR1`"]
462 #[inline]
463 pub fn is_itr1(&self) -> bool {
464 *self == TSR::ITR1
465 }
466 #[doc = "Checks if the value of the field is `ITR2`"]
467 #[inline]
468 pub fn is_itr2(&self) -> bool {
469 *self == TSR::ITR2
470 }
471 #[doc = "Checks if the value of the field is `TI1F_ED`"]
472 #[inline]
473 pub fn is_ti1f_ed(&self) -> bool {
474 *self == TSR::TI1F_ED
475 }
476 #[doc = "Checks if the value of the field is `TI1FP1`"]
477 #[inline]
478 pub fn is_ti1fp1(&self) -> bool {
479 *self == TSR::TI1FP1
480 }
481 #[doc = "Checks if the value of the field is `TI2FP2`"]
482 #[inline]
483 pub fn is_ti2fp2(&self) -> bool {
484 *self == TSR::TI2FP2
485 }
486 #[doc = "Checks if the value of the field is `ETRF`"]
487 #[inline]
488 pub fn is_etrf(&self) -> bool {
489 *self == TSR::ETRF
490 }
491}
492#[doc = "Possible values of the field `SMS`"]
493#[derive(Clone, Copy, Debug, PartialEq)]
494pub enum SMSR {
495 #[doc = "Slave mode disabled - if CEN = \u{2018}1 then the prescaler is clocked directly by the internal clock."]
496 DISABLED,
497 #[doc = "Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level."]
498 ENCODER_MODE_1,
499 #[doc = "Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level."]
500 ENCODER_MODE_2,
501 #[doc = "Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input."]
502 ENCODER_MODE_3,
503 #[doc = "Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers."]
504 RESET_MODE,
505 #[doc = "Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled."]
506 GATED_MODE,
507 #[doc = "Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled."]
508 TRIGGER_MODE,
509 #[doc = "External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter."]
510 EXT_CLOCK_MODE,
511}
512impl SMSR {
513 #[doc = r" Value of the field as raw bits"]
514 #[inline]
515 pub fn bits(&self) -> u8 {
516 match *self {
517 SMSR::DISABLED => 0,
518 SMSR::ENCODER_MODE_1 => 1,
519 SMSR::ENCODER_MODE_2 => 2,
520 SMSR::ENCODER_MODE_3 => 3,
521 SMSR::RESET_MODE => 4,
522 SMSR::GATED_MODE => 5,
523 SMSR::TRIGGER_MODE => 6,
524 SMSR::EXT_CLOCK_MODE => 7,
525 }
526 }
527 #[allow(missing_docs)]
528 #[doc(hidden)]
529 #[inline]
530 pub fn _from(value: u8) -> SMSR {
531 match value {
532 0 => SMSR::DISABLED,
533 1 => SMSR::ENCODER_MODE_1,
534 2 => SMSR::ENCODER_MODE_2,
535 3 => SMSR::ENCODER_MODE_3,
536 4 => SMSR::RESET_MODE,
537 5 => SMSR::GATED_MODE,
538 6 => SMSR::TRIGGER_MODE,
539 7 => SMSR::EXT_CLOCK_MODE,
540 _ => unreachable!(),
541 }
542 }
543 #[doc = "Checks if the value of the field is `DISABLED`"]
544 #[inline]
545 pub fn is_disabled(&self) -> bool {
546 *self == SMSR::DISABLED
547 }
548 #[doc = "Checks if the value of the field is `ENCODER_MODE_1`"]
549 #[inline]
550 pub fn is_encoder_mode_1(&self) -> bool {
551 *self == SMSR::ENCODER_MODE_1
552 }
553 #[doc = "Checks if the value of the field is `ENCODER_MODE_2`"]
554 #[inline]
555 pub fn is_encoder_mode_2(&self) -> bool {
556 *self == SMSR::ENCODER_MODE_2
557 }
558 #[doc = "Checks if the value of the field is `ENCODER_MODE_3`"]
559 #[inline]
560 pub fn is_encoder_mode_3(&self) -> bool {
561 *self == SMSR::ENCODER_MODE_3
562 }
563 #[doc = "Checks if the value of the field is `RESET_MODE`"]
564 #[inline]
565 pub fn is_reset_mode(&self) -> bool {
566 *self == SMSR::RESET_MODE
567 }
568 #[doc = "Checks if the value of the field is `GATED_MODE`"]
569 #[inline]
570 pub fn is_gated_mode(&self) -> bool {
571 *self == SMSR::GATED_MODE
572 }
573 #[doc = "Checks if the value of the field is `TRIGGER_MODE`"]
574 #[inline]
575 pub fn is_trigger_mode(&self) -> bool {
576 *self == SMSR::TRIGGER_MODE
577 }
578 #[doc = "Checks if the value of the field is `EXT_CLOCK_MODE`"]
579 #[inline]
580 pub fn is_ext_clock_mode(&self) -> bool {
581 *self == SMSR::EXT_CLOCK_MODE
582 }
583}
584#[doc = "Values that can be written to the field `ETP`"]
585pub enum ETPW {
586 #[doc = "ETR is noninverted, active at high level or rising edge"]
587 NOTINVERTED,
588 #[doc = "ETR is inverted, active at low level or falling edge"]
589 INVERTED,
590}
591impl ETPW {
592 #[allow(missing_docs)]
593 #[doc(hidden)]
594 #[inline]
595 pub fn _bits(&self) -> bool {
596 match *self {
597 ETPW::NOTINVERTED => false,
598 ETPW::INVERTED => true,
599 }
600 }
601}
602#[doc = r" Proxy"]
603pub struct _ETPW<'a> {
604 w: &'a mut W,
605}
606impl<'a> _ETPW<'a> {
607 #[doc = r" Writes `variant` to the field"]
608 #[inline]
609 pub fn variant(self, variant: ETPW) -> &'a mut W {
610 {
611 self.bit(variant._bits())
612 }
613 }
614 #[doc = "ETR is noninverted, active at high level or rising edge"]
615 #[inline]
616 pub fn not_inverted(self) -> &'a mut W {
617 self.variant(ETPW::NOTINVERTED)
618 }
619 #[doc = "ETR is inverted, active at low level or falling edge"]
620 #[inline]
621 pub fn inverted(self) -> &'a mut W {
622 self.variant(ETPW::INVERTED)
623 }
624 #[doc = r" Sets the field bit"]
625 pub fn set_bit(self) -> &'a mut W {
626 self.bit(true)
627 }
628 #[doc = r" Clears the field bit"]
629 pub fn clear_bit(self) -> &'a mut W {
630 self.bit(false)
631 }
632 #[doc = r" Writes raw bits to the field"]
633 #[inline]
634 pub fn bit(self, value: bool) -> &'a mut W {
635 const MASK: bool = true;
636 const OFFSET: u8 = 15;
637 self.w.bits &= !((MASK as u32) << OFFSET);
638 self.w.bits |= ((value & MASK) as u32) << OFFSET;
639 self.w
640 }
641}
642#[doc = "Values that can be written to the field `ECE`"]
643pub enum ECEW {
644 #[doc = "External clock mode 2 disabled"]
645 DISABLED,
646 #[doc = "External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal."]
647 ENABLED,
648}
649impl ECEW {
650 #[allow(missing_docs)]
651 #[doc(hidden)]
652 #[inline]
653 pub fn _bits(&self) -> bool {
654 match *self {
655 ECEW::DISABLED => false,
656 ECEW::ENABLED => true,
657 }
658 }
659}
660#[doc = r" Proxy"]
661pub struct _ECEW<'a> {
662 w: &'a mut W,
663}
664impl<'a> _ECEW<'a> {
665 #[doc = r" Writes `variant` to the field"]
666 #[inline]
667 pub fn variant(self, variant: ECEW) -> &'a mut W {
668 {
669 self.bit(variant._bits())
670 }
671 }
672 #[doc = "External clock mode 2 disabled"]
673 #[inline]
674 pub fn disabled(self) -> &'a mut W {
675 self.variant(ECEW::DISABLED)
676 }
677 #[doc = "External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal."]
678 #[inline]
679 pub fn enabled(self) -> &'a mut W {
680 self.variant(ECEW::ENABLED)
681 }
682 #[doc = r" Sets the field bit"]
683 pub fn set_bit(self) -> &'a mut W {
684 self.bit(true)
685 }
686 #[doc = r" Clears the field bit"]
687 pub fn clear_bit(self) -> &'a mut W {
688 self.bit(false)
689 }
690 #[doc = r" Writes raw bits to the field"]
691 #[inline]
692 pub fn bit(self, value: bool) -> &'a mut W {
693 const MASK: bool = true;
694 const OFFSET: u8 = 14;
695 self.w.bits &= !((MASK as u32) << OFFSET);
696 self.w.bits |= ((value & MASK) as u32) << OFFSET;
697 self.w
698 }
699}
700#[doc = "Values that can be written to the field `ETPS`"]
701pub enum ETPSW {
702 #[doc = "Prescaler OFF"]
703 NODIV,
704 #[doc = "ETRP frequency divided by 2"]
705 DIV2,
706 #[doc = "ETRP frequency divided by 4"]
707 DIV4,
708 #[doc = "ETRP frequency divided by 8"]
709 DIV8,
710}
711impl ETPSW {
712 #[allow(missing_docs)]
713 #[doc(hidden)]
714 #[inline]
715 pub fn _bits(&self) -> u8 {
716 match *self {
717 ETPSW::NODIV => 0,
718 ETPSW::DIV2 => 1,
719 ETPSW::DIV4 => 2,
720 ETPSW::DIV8 => 3,
721 }
722 }
723}
724#[doc = r" Proxy"]
725pub struct _ETPSW<'a> {
726 w: &'a mut W,
727}
728impl<'a> _ETPSW<'a> {
729 #[doc = r" Writes `variant` to the field"]
730 #[inline]
731 pub fn variant(self, variant: ETPSW) -> &'a mut W {
732 {
733 self.bits(variant._bits())
734 }
735 }
736 #[doc = "Prescaler OFF"]
737 #[inline]
738 pub fn no_div(self) -> &'a mut W {
739 self.variant(ETPSW::NODIV)
740 }
741 #[doc = "ETRP frequency divided by 2"]
742 #[inline]
743 pub fn div2(self) -> &'a mut W {
744 self.variant(ETPSW::DIV2)
745 }
746 #[doc = "ETRP frequency divided by 4"]
747 #[inline]
748 pub fn div4(self) -> &'a mut W {
749 self.variant(ETPSW::DIV4)
750 }
751 #[doc = "ETRP frequency divided by 8"]
752 #[inline]
753 pub fn div8(self) -> &'a mut W {
754 self.variant(ETPSW::DIV8)
755 }
756 #[doc = r" Writes raw bits to the field"]
757 #[inline]
758 pub fn bits(self, value: u8) -> &'a mut W {
759 const MASK: u8 = 3;
760 const OFFSET: u8 = 12;
761 self.w.bits &= !((MASK as u32) << OFFSET);
762 self.w.bits |= ((value & MASK) as u32) << OFFSET;
763 self.w
764 }
765}
766#[doc = "Values that can be written to the field `ETF`"]
767pub enum ETFW {
768 #[doc = "No filter, sampling is done at fDTS"]
769 NOFILTER,
770 #[doc = "fSAMPLING=fCK_INT, N=2"]
771 FCK_INT_N2,
772 #[doc = "fSAMPLING=fCK_INT, N=4"]
773 FCK_INT_N4,
774 #[doc = "fSAMPLING=fCK_INT, N=8"]
775 FCK_INT_N8,
776 #[doc = "fSAMPLING=fDTS/2, N=6"]
777 FDTS_DIV2_N6,
778 #[doc = "fSAMPLING=fDTS/2, N=8"]
779 FDTS_DIV2_N8,
780 #[doc = "fSAMPLING=fDTS/4, N=6"]
781 FDTS_DIV4_N6,
782 #[doc = "fSAMPLING=fDTS/4, N=8"]
783 FDTS_DIV4_N8,
784 #[doc = "fSAMPLING=fDTS/8, N=6"]
785 FDTS_DIV8_N6,
786 #[doc = "fSAMPLING=fDTS/8, N=8"]
787 FDTS_DIV8_N8,
788 #[doc = "fSAMPLING=fDTS/16, N=5"]
789 FDTS_DIV16_N5,
790 #[doc = "fSAMPLING=fDTS/16, N=6"]
791 FDTS_DIV16_N6,
792 #[doc = "fSAMPLING=fDTS/16, N=8"]
793 FDTS_DIV16_N8,
794 #[doc = "fSAMPLING=fDTS/32, N=5"]
795 FDTS_DIV32_N5,
796 #[doc = "fSAMPLING=fDTS/32, N=6"]
797 FDTS_DIV32_N6,
798 #[doc = "fSAMPLING=fDTS/32, N=8"]
799 FDTS_DIV32_N8,
800}
801impl ETFW {
802 #[allow(missing_docs)]
803 #[doc(hidden)]
804 #[inline]
805 pub fn _bits(&self) -> u8 {
806 match *self {
807 ETFW::NOFILTER => 0,
808 ETFW::FCK_INT_N2 => 1,
809 ETFW::FCK_INT_N4 => 2,
810 ETFW::FCK_INT_N8 => 3,
811 ETFW::FDTS_DIV2_N6 => 4,
812 ETFW::FDTS_DIV2_N8 => 5,
813 ETFW::FDTS_DIV4_N6 => 6,
814 ETFW::FDTS_DIV4_N8 => 7,
815 ETFW::FDTS_DIV8_N6 => 8,
816 ETFW::FDTS_DIV8_N8 => 9,
817 ETFW::FDTS_DIV16_N5 => 10,
818 ETFW::FDTS_DIV16_N6 => 11,
819 ETFW::FDTS_DIV16_N8 => 12,
820 ETFW::FDTS_DIV32_N5 => 13,
821 ETFW::FDTS_DIV32_N6 => 14,
822 ETFW::FDTS_DIV32_N8 => 15,
823 }
824 }
825}
826#[doc = r" Proxy"]
827pub struct _ETFW<'a> {
828 w: &'a mut W,
829}
830impl<'a> _ETFW<'a> {
831 #[doc = r" Writes `variant` to the field"]
832 #[inline]
833 pub fn variant(self, variant: ETFW) -> &'a mut W {
834 {
835 self.bits(variant._bits())
836 }
837 }
838 #[doc = "No filter, sampling is done at fDTS"]
839 #[inline]
840 pub fn no_filter(self) -> &'a mut W {
841 self.variant(ETFW::NOFILTER)
842 }
843 #[doc = "fSAMPLING=fCK_INT, N=2"]
844 #[inline]
845 pub fn fck_int_n2(self) -> &'a mut W {
846 self.variant(ETFW::FCK_INT_N2)
847 }
848 #[doc = "fSAMPLING=fCK_INT, N=4"]
849 #[inline]
850 pub fn fck_int_n4(self) -> &'a mut W {
851 self.variant(ETFW::FCK_INT_N4)
852 }
853 #[doc = "fSAMPLING=fCK_INT, N=8"]
854 #[inline]
855 pub fn fck_int_n8(self) -> &'a mut W {
856 self.variant(ETFW::FCK_INT_N8)
857 }
858 #[doc = "fSAMPLING=fDTS/2, N=6"]
859 #[inline]
860 pub fn fdts_div2_n6(self) -> &'a mut W {
861 self.variant(ETFW::FDTS_DIV2_N6)
862 }
863 #[doc = "fSAMPLING=fDTS/2, N=8"]
864 #[inline]
865 pub fn fdts_div2_n8(self) -> &'a mut W {
866 self.variant(ETFW::FDTS_DIV2_N8)
867 }
868 #[doc = "fSAMPLING=fDTS/4, N=6"]
869 #[inline]
870 pub fn fdts_div4_n6(self) -> &'a mut W {
871 self.variant(ETFW::FDTS_DIV4_N6)
872 }
873 #[doc = "fSAMPLING=fDTS/4, N=8"]
874 #[inline]
875 pub fn fdts_div4_n8(self) -> &'a mut W {
876 self.variant(ETFW::FDTS_DIV4_N8)
877 }
878 #[doc = "fSAMPLING=fDTS/8, N=6"]
879 #[inline]
880 pub fn fdts_div8_n6(self) -> &'a mut W {
881 self.variant(ETFW::FDTS_DIV8_N6)
882 }
883 #[doc = "fSAMPLING=fDTS/8, N=8"]
884 #[inline]
885 pub fn fdts_div8_n8(self) -> &'a mut W {
886 self.variant(ETFW::FDTS_DIV8_N8)
887 }
888 #[doc = "fSAMPLING=fDTS/16, N=5"]
889 #[inline]
890 pub fn fdts_div16_n5(self) -> &'a mut W {
891 self.variant(ETFW::FDTS_DIV16_N5)
892 }
893 #[doc = "fSAMPLING=fDTS/16, N=6"]
894 #[inline]
895 pub fn fdts_div16_n6(self) -> &'a mut W {
896 self.variant(ETFW::FDTS_DIV16_N6)
897 }
898 #[doc = "fSAMPLING=fDTS/16, N=8"]
899 #[inline]
900 pub fn fdts_div16_n8(self) -> &'a mut W {
901 self.variant(ETFW::FDTS_DIV16_N8)
902 }
903 #[doc = "fSAMPLING=fDTS/32, N=5"]
904 #[inline]
905 pub fn fdts_div32_n5(self) -> &'a mut W {
906 self.variant(ETFW::FDTS_DIV32_N5)
907 }
908 #[doc = "fSAMPLING=fDTS/32, N=6"]
909 #[inline]
910 pub fn fdts_div32_n6(self) -> &'a mut W {
911 self.variant(ETFW::FDTS_DIV32_N6)
912 }
913 #[doc = "fSAMPLING=fDTS/32, N=8"]
914 #[inline]
915 pub fn fdts_div32_n8(self) -> &'a mut W {
916 self.variant(ETFW::FDTS_DIV32_N8)
917 }
918 #[doc = r" Writes raw bits to the field"]
919 #[inline]
920 pub fn bits(self, value: u8) -> &'a mut W {
921 const MASK: u8 = 15;
922 const OFFSET: u8 = 8;
923 self.w.bits &= !((MASK as u32) << OFFSET);
924 self.w.bits |= ((value & MASK) as u32) << OFFSET;
925 self.w
926 }
927}
928#[doc = "Values that can be written to the field `MSM`"]
929pub enum MSMW {
930 #[doc = "No action"]
931 NOSYNC,
932 #[doc = "The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."]
933 SYNC,
934}
935impl MSMW {
936 #[allow(missing_docs)]
937 #[doc(hidden)]
938 #[inline]
939 pub fn _bits(&self) -> bool {
940 match *self {
941 MSMW::NOSYNC => false,
942 MSMW::SYNC => true,
943 }
944 }
945}
946#[doc = r" Proxy"]
947pub struct _MSMW<'a> {
948 w: &'a mut W,
949}
950impl<'a> _MSMW<'a> {
951 #[doc = r" Writes `variant` to the field"]
952 #[inline]
953 pub fn variant(self, variant: MSMW) -> &'a mut W {
954 {
955 self.bit(variant._bits())
956 }
957 }
958 #[doc = "No action"]
959 #[inline]
960 pub fn no_sync(self) -> &'a mut W {
961 self.variant(MSMW::NOSYNC)
962 }
963 #[doc = "The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."]
964 #[inline]
965 pub fn sync(self) -> &'a mut W {
966 self.variant(MSMW::SYNC)
967 }
968 #[doc = r" Sets the field bit"]
969 pub fn set_bit(self) -> &'a mut W {
970 self.bit(true)
971 }
972 #[doc = r" Clears the field bit"]
973 pub fn clear_bit(self) -> &'a mut W {
974 self.bit(false)
975 }
976 #[doc = r" Writes raw bits to the field"]
977 #[inline]
978 pub fn bit(self, value: bool) -> &'a mut W {
979 const MASK: bool = true;
980 const OFFSET: u8 = 7;
981 self.w.bits &= !((MASK as u32) << OFFSET);
982 self.w.bits |= ((value & MASK) as u32) << OFFSET;
983 self.w
984 }
985}
986#[doc = "Values that can be written to the field `TS`"]
987pub enum TSW {
988 #[doc = "Internal Trigger 0 (ITR0)"]
989 ITR0,
990 #[doc = "Internal Trigger 1 (ITR1)"]
991 ITR1,
992 #[doc = "Internal Trigger 2 (ITR2)"]
993 ITR2,
994 #[doc = "TI1 Edge Detector (TI1F_ED)"]
995 TI1F_ED,
996 #[doc = "Filtered Timer Input 1 (TI1FP1)"]
997 TI1FP1,
998 #[doc = "Filtered Timer Input 2 (TI2FP2)"]
999 TI2FP2,
1000 #[doc = "External Trigger input (ETRF)"]
1001 ETRF,
1002}
1003impl TSW {
1004 #[allow(missing_docs)]
1005 #[doc(hidden)]
1006 #[inline]
1007 pub fn _bits(&self) -> u8 {
1008 match *self {
1009 TSW::ITR0 => 0,
1010 TSW::ITR1 => 1,
1011 TSW::ITR2 => 2,
1012 TSW::TI1F_ED => 4,
1013 TSW::TI1FP1 => 5,
1014 TSW::TI2FP2 => 6,
1015 TSW::ETRF => 7,
1016 }
1017 }
1018}
1019#[doc = r" Proxy"]
1020pub struct _TSW<'a> {
1021 w: &'a mut W,
1022}
1023impl<'a> _TSW<'a> {
1024 #[doc = r" Writes `variant` to the field"]
1025 #[inline]
1026 pub fn variant(self, variant: TSW) -> &'a mut W {
1027 unsafe { self.bits(variant._bits()) }
1028 }
1029 #[doc = "Internal Trigger 0 (ITR0)"]
1030 #[inline]
1031 pub fn itr0(self) -> &'a mut W {
1032 self.variant(TSW::ITR0)
1033 }
1034 #[doc = "Internal Trigger 1 (ITR1)"]
1035 #[inline]
1036 pub fn itr1(self) -> &'a mut W {
1037 self.variant(TSW::ITR1)
1038 }
1039 #[doc = "Internal Trigger 2 (ITR2)"]
1040 #[inline]
1041 pub fn itr2(self) -> &'a mut W {
1042 self.variant(TSW::ITR2)
1043 }
1044 #[doc = "TI1 Edge Detector (TI1F_ED)"]
1045 #[inline]
1046 pub fn ti1f_ed(self) -> &'a mut W {
1047 self.variant(TSW::TI1F_ED)
1048 }
1049 #[doc = "Filtered Timer Input 1 (TI1FP1)"]
1050 #[inline]
1051 pub fn ti1fp1(self) -> &'a mut W {
1052 self.variant(TSW::TI1FP1)
1053 }
1054 #[doc = "Filtered Timer Input 2 (TI2FP2)"]
1055 #[inline]
1056 pub fn ti2fp2(self) -> &'a mut W {
1057 self.variant(TSW::TI2FP2)
1058 }
1059 #[doc = "External Trigger input (ETRF)"]
1060 #[inline]
1061 pub fn etrf(self) -> &'a mut W {
1062 self.variant(TSW::ETRF)
1063 }
1064 #[doc = r" Writes raw bits to the field"]
1065 #[inline]
1066 pub unsafe fn bits(self, value: u8) -> &'a mut W {
1067 const MASK: u8 = 7;
1068 const OFFSET: u8 = 4;
1069 self.w.bits &= !((MASK as u32) << OFFSET);
1070 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1071 self.w
1072 }
1073}
1074#[doc = "Values that can be written to the field `SMS`"]
1075pub enum SMSW {
1076 #[doc = "Slave mode disabled - if CEN = \u{2018}1 then the prescaler is clocked directly by the internal clock."]
1077 DISABLED,
1078 #[doc = "Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level."]
1079 ENCODER_MODE_1,
1080 #[doc = "Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level."]
1081 ENCODER_MODE_2,
1082 #[doc = "Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input."]
1083 ENCODER_MODE_3,
1084 #[doc = "Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers."]
1085 RESET_MODE,
1086 #[doc = "Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled."]
1087 GATED_MODE,
1088 #[doc = "Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled."]
1089 TRIGGER_MODE,
1090 #[doc = "External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter."]
1091 EXT_CLOCK_MODE,
1092}
1093impl SMSW {
1094 #[allow(missing_docs)]
1095 #[doc(hidden)]
1096 #[inline]
1097 pub fn _bits(&self) -> u8 {
1098 match *self {
1099 SMSW::DISABLED => 0,
1100 SMSW::ENCODER_MODE_1 => 1,
1101 SMSW::ENCODER_MODE_2 => 2,
1102 SMSW::ENCODER_MODE_3 => 3,
1103 SMSW::RESET_MODE => 4,
1104 SMSW::GATED_MODE => 5,
1105 SMSW::TRIGGER_MODE => 6,
1106 SMSW::EXT_CLOCK_MODE => 7,
1107 }
1108 }
1109}
1110#[doc = r" Proxy"]
1111pub struct _SMSW<'a> {
1112 w: &'a mut W,
1113}
1114impl<'a> _SMSW<'a> {
1115 #[doc = r" Writes `variant` to the field"]
1116 #[inline]
1117 pub fn variant(self, variant: SMSW) -> &'a mut W {
1118 {
1119 self.bits(variant._bits())
1120 }
1121 }
1122 #[doc = "Slave mode disabled - if CEN = \u{2018}1 then the prescaler is clocked directly by the internal clock."]
1123 #[inline]
1124 pub fn disabled(self) -> &'a mut W {
1125 self.variant(SMSW::DISABLED)
1126 }
1127 #[doc = "Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level."]
1128 #[inline]
1129 pub fn encoder_mode_1(self) -> &'a mut W {
1130 self.variant(SMSW::ENCODER_MODE_1)
1131 }
1132 #[doc = "Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level."]
1133 #[inline]
1134 pub fn encoder_mode_2(self) -> &'a mut W {
1135 self.variant(SMSW::ENCODER_MODE_2)
1136 }
1137 #[doc = "Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input."]
1138 #[inline]
1139 pub fn encoder_mode_3(self) -> &'a mut W {
1140 self.variant(SMSW::ENCODER_MODE_3)
1141 }
1142 #[doc = "Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers."]
1143 #[inline]
1144 pub fn reset_mode(self) -> &'a mut W {
1145 self.variant(SMSW::RESET_MODE)
1146 }
1147 #[doc = "Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled."]
1148 #[inline]
1149 pub fn gated_mode(self) -> &'a mut W {
1150 self.variant(SMSW::GATED_MODE)
1151 }
1152 #[doc = "Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled."]
1153 #[inline]
1154 pub fn trigger_mode(self) -> &'a mut W {
1155 self.variant(SMSW::TRIGGER_MODE)
1156 }
1157 #[doc = "External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter."]
1158 #[inline]
1159 pub fn ext_clock_mode(self) -> &'a mut W {
1160 self.variant(SMSW::EXT_CLOCK_MODE)
1161 }
1162 #[doc = r" Writes raw bits to the field"]
1163 #[inline]
1164 pub fn bits(self, value: u8) -> &'a mut W {
1165 const MASK: u8 = 7;
1166 const OFFSET: u8 = 0;
1167 self.w.bits &= !((MASK as u32) << OFFSET);
1168 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1169 self.w
1170 }
1171}
1172impl R {
1173 #[doc = r" Value of the register as raw bits"]
1174 #[inline]
1175 pub fn bits(&self) -> u32 {
1176 self.bits
1177 }
1178 #[doc = "Bit 15 - External trigger polarity"]
1179 #[inline]
1180 pub fn etp(&self) -> ETPR {
1181 ETPR::_from({
1182 const MASK: bool = true;
1183 const OFFSET: u8 = 15;
1184 ((self.bits >> OFFSET) & MASK as u32) != 0
1185 })
1186 }
1187 #[doc = "Bit 14 - External clock enable"]
1188 #[inline]
1189 pub fn ece(&self) -> ECER {
1190 ECER::_from({
1191 const MASK: bool = true;
1192 const OFFSET: u8 = 14;
1193 ((self.bits >> OFFSET) & MASK as u32) != 0
1194 })
1195 }
1196 #[doc = "Bits 12:13 - External trigger prescaler"]
1197 #[inline]
1198 pub fn etps(&self) -> ETPSR {
1199 ETPSR::_from({
1200 const MASK: u8 = 3;
1201 const OFFSET: u8 = 12;
1202 ((self.bits >> OFFSET) & MASK as u32) as u8
1203 })
1204 }
1205 #[doc = "Bits 8:11 - External trigger filter"]
1206 #[inline]
1207 pub fn etf(&self) -> ETFR {
1208 ETFR::_from({
1209 const MASK: u8 = 15;
1210 const OFFSET: u8 = 8;
1211 ((self.bits >> OFFSET) & MASK as u32) as u8
1212 })
1213 }
1214 #[doc = "Bit 7 - Master/Slave mode"]
1215 #[inline]
1216 pub fn msm(&self) -> MSMR {
1217 MSMR::_from({
1218 const MASK: bool = true;
1219 const OFFSET: u8 = 7;
1220 ((self.bits >> OFFSET) & MASK as u32) != 0
1221 })
1222 }
1223 #[doc = "Bits 4:6 - Trigger selection"]
1224 #[inline]
1225 pub fn ts(&self) -> TSR {
1226 TSR::_from({
1227 const MASK: u8 = 7;
1228 const OFFSET: u8 = 4;
1229 ((self.bits >> OFFSET) & MASK as u32) as u8
1230 })
1231 }
1232 #[doc = "Bits 0:2 - Slave mode selection"]
1233 #[inline]
1234 pub fn sms(&self) -> SMSR {
1235 SMSR::_from({
1236 const MASK: u8 = 7;
1237 const OFFSET: u8 = 0;
1238 ((self.bits >> OFFSET) & MASK as u32) as u8
1239 })
1240 }
1241}
1242impl W {
1243 #[doc = r" Reset value of the register"]
1244 #[inline]
1245 pub fn reset_value() -> W {
1246 W { bits: 0 }
1247 }
1248 #[doc = r" Writes raw bits to the register"]
1249 #[inline]
1250 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1251 self.bits = bits;
1252 self
1253 }
1254 #[doc = "Bit 15 - External trigger polarity"]
1255 #[inline]
1256 pub fn etp(&mut self) -> _ETPW {
1257 _ETPW { w: self }
1258 }
1259 #[doc = "Bit 14 - External clock enable"]
1260 #[inline]
1261 pub fn ece(&mut self) -> _ECEW {
1262 _ECEW { w: self }
1263 }
1264 #[doc = "Bits 12:13 - External trigger prescaler"]
1265 #[inline]
1266 pub fn etps(&mut self) -> _ETPSW {
1267 _ETPSW { w: self }
1268 }
1269 #[doc = "Bits 8:11 - External trigger filter"]
1270 #[inline]
1271 pub fn etf(&mut self) -> _ETFW {
1272 _ETFW { w: self }
1273 }
1274 #[doc = "Bit 7 - Master/Slave mode"]
1275 #[inline]
1276 pub fn msm(&mut self) -> _MSMW {
1277 _MSMW { w: self }
1278 }
1279 #[doc = "Bits 4:6 - Trigger selection"]
1280 #[inline]
1281 pub fn ts(&mut self) -> _TSW {
1282 _TSW { w: self }
1283 }
1284 #[doc = "Bits 0:2 - Slave mode selection"]
1285 #[inline]
1286 pub fn sms(&mut self) -> _SMSW {
1287 _SMSW { w: self }
1288 }
1289}