stm32l4x2_pac/tim2/
egr.rs

1#[doc = r" Value to write to the register"]
2pub struct W {
3    bits: u32,
4}
5impl super::EGR {
6    #[doc = r" Writes to the register"]
7    #[inline]
8    pub fn write<F>(&self, f: F)
9    where
10        F: FnOnce(&mut W) -> &mut W,
11    {
12        let mut w = W::reset_value();
13        f(&mut w);
14        self.register.set(w.bits);
15    }
16}
17#[doc = "Values that can be written to the field `TG`"]
18pub enum TGW {
19    #[doc = "The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled."]
20    TRIGGER,
21}
22impl TGW {
23    #[allow(missing_docs)]
24    #[doc(hidden)]
25    #[inline]
26    pub fn _bits(&self) -> bool {
27        match *self {
28            TGW::TRIGGER => true,
29        }
30    }
31}
32#[doc = r" Proxy"]
33pub struct _TGW<'a> {
34    w: &'a mut W,
35}
36impl<'a> _TGW<'a> {
37    #[doc = r" Writes `variant` to the field"]
38    #[inline]
39    pub fn variant(self, variant: TGW) -> &'a mut W {
40        {
41            self.bit(variant._bits())
42        }
43    }
44    #[doc = "The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled."]
45    #[inline]
46    pub fn trigger(self) -> &'a mut W {
47        self.variant(TGW::TRIGGER)
48    }
49    #[doc = r" Sets the field bit"]
50    pub fn set_bit(self) -> &'a mut W {
51        self.bit(true)
52    }
53    #[doc = r" Clears the field bit"]
54    pub fn clear_bit(self) -> &'a mut W {
55        self.bit(false)
56    }
57    #[doc = r" Writes raw bits to the field"]
58    #[inline]
59    pub fn bit(self, value: bool) -> &'a mut W {
60        const MASK: bool = true;
61        const OFFSET: u8 = 6;
62        self.w.bits &= !((MASK as u32) << OFFSET);
63        self.w.bits |= ((value & MASK) as u32) << OFFSET;
64        self.w
65    }
66}
67#[doc = "Values that can be written to the field `CC4G`"]
68pub enum CC4GW {
69    #[doc = "If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register."]
70    TRIGGER,
71}
72impl CC4GW {
73    #[allow(missing_docs)]
74    #[doc(hidden)]
75    #[inline]
76    pub fn _bits(&self) -> bool {
77        match *self {
78            CC4GW::TRIGGER => true,
79        }
80    }
81}
82#[doc = r" Proxy"]
83pub struct _CC4GW<'a> {
84    w: &'a mut W,
85}
86impl<'a> _CC4GW<'a> {
87    #[doc = r" Writes `variant` to the field"]
88    #[inline]
89    pub fn variant(self, variant: CC4GW) -> &'a mut W {
90        {
91            self.bit(variant._bits())
92        }
93    }
94    #[doc = "If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register."]
95    #[inline]
96    pub fn trigger(self) -> &'a mut W {
97        self.variant(CC4GW::TRIGGER)
98    }
99    #[doc = r" Sets the field bit"]
100    pub fn set_bit(self) -> &'a mut W {
101        self.bit(true)
102    }
103    #[doc = r" Clears the field bit"]
104    pub fn clear_bit(self) -> &'a mut W {
105        self.bit(false)
106    }
107    #[doc = r" Writes raw bits to the field"]
108    #[inline]
109    pub fn bit(self, value: bool) -> &'a mut W {
110        const MASK: bool = true;
111        const OFFSET: u8 = 4;
112        self.w.bits &= !((MASK as u32) << OFFSET);
113        self.w.bits |= ((value & MASK) as u32) << OFFSET;
114        self.w
115    }
116}
117#[doc = "Values that can be written to the field `CC3G`"]
118pub type CC3GW = CC4GW;
119#[doc = r" Proxy"]
120pub struct _CC3GW<'a> {
121    w: &'a mut W,
122}
123impl<'a> _CC3GW<'a> {
124    #[doc = r" Writes `variant` to the field"]
125    #[inline]
126    pub fn variant(self, variant: CC3GW) -> &'a mut W {
127        {
128            self.bit(variant._bits())
129        }
130    }
131    #[doc = "If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register."]
132    #[inline]
133    pub fn trigger(self) -> &'a mut W {
134        self.variant(CC4GW::TRIGGER)
135    }
136    #[doc = r" Sets the field bit"]
137    pub fn set_bit(self) -> &'a mut W {
138        self.bit(true)
139    }
140    #[doc = r" Clears the field bit"]
141    pub fn clear_bit(self) -> &'a mut W {
142        self.bit(false)
143    }
144    #[doc = r" Writes raw bits to the field"]
145    #[inline]
146    pub fn bit(self, value: bool) -> &'a mut W {
147        const MASK: bool = true;
148        const OFFSET: u8 = 3;
149        self.w.bits &= !((MASK as u32) << OFFSET);
150        self.w.bits |= ((value & MASK) as u32) << OFFSET;
151        self.w
152    }
153}
154#[doc = "Values that can be written to the field `CC2G`"]
155pub type CC2GW = CC4GW;
156#[doc = r" Proxy"]
157pub struct _CC2GW<'a> {
158    w: &'a mut W,
159}
160impl<'a> _CC2GW<'a> {
161    #[doc = r" Writes `variant` to the field"]
162    #[inline]
163    pub fn variant(self, variant: CC2GW) -> &'a mut W {
164        {
165            self.bit(variant._bits())
166        }
167    }
168    #[doc = "If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register."]
169    #[inline]
170    pub fn trigger(self) -> &'a mut W {
171        self.variant(CC4GW::TRIGGER)
172    }
173    #[doc = r" Sets the field bit"]
174    pub fn set_bit(self) -> &'a mut W {
175        self.bit(true)
176    }
177    #[doc = r" Clears the field bit"]
178    pub fn clear_bit(self) -> &'a mut W {
179        self.bit(false)
180    }
181    #[doc = r" Writes raw bits to the field"]
182    #[inline]
183    pub fn bit(self, value: bool) -> &'a mut W {
184        const MASK: bool = true;
185        const OFFSET: u8 = 2;
186        self.w.bits &= !((MASK as u32) << OFFSET);
187        self.w.bits |= ((value & MASK) as u32) << OFFSET;
188        self.w
189    }
190}
191#[doc = "Values that can be written to the field `CC1G`"]
192pub type CC1GW = CC4GW;
193#[doc = r" Proxy"]
194pub struct _CC1GW<'a> {
195    w: &'a mut W,
196}
197impl<'a> _CC1GW<'a> {
198    #[doc = r" Writes `variant` to the field"]
199    #[inline]
200    pub fn variant(self, variant: CC1GW) -> &'a mut W {
201        {
202            self.bit(variant._bits())
203        }
204    }
205    #[doc = "If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register."]
206    #[inline]
207    pub fn trigger(self) -> &'a mut W {
208        self.variant(CC4GW::TRIGGER)
209    }
210    #[doc = r" Sets the field bit"]
211    pub fn set_bit(self) -> &'a mut W {
212        self.bit(true)
213    }
214    #[doc = r" Clears the field bit"]
215    pub fn clear_bit(self) -> &'a mut W {
216        self.bit(false)
217    }
218    #[doc = r" Writes raw bits to the field"]
219    #[inline]
220    pub fn bit(self, value: bool) -> &'a mut W {
221        const MASK: bool = true;
222        const OFFSET: u8 = 1;
223        self.w.bits &= !((MASK as u32) << OFFSET);
224        self.w.bits |= ((value & MASK) as u32) << OFFSET;
225        self.w
226    }
227}
228#[doc = "Values that can be written to the field `UG`"]
229pub enum UGW {
230    #[doc = "Re-initializes the timer counter and generates an update of the reigsters."]
231    UPDATE,
232}
233impl UGW {
234    #[allow(missing_docs)]
235    #[doc(hidden)]
236    #[inline]
237    pub fn _bits(&self) -> bool {
238        match *self {
239            UGW::UPDATE => true,
240        }
241    }
242}
243#[doc = r" Proxy"]
244pub struct _UGW<'a> {
245    w: &'a mut W,
246}
247impl<'a> _UGW<'a> {
248    #[doc = r" Writes `variant` to the field"]
249    #[inline]
250    pub fn variant(self, variant: UGW) -> &'a mut W {
251        {
252            self.bit(variant._bits())
253        }
254    }
255    #[doc = "Re-initializes the timer counter and generates an update of the reigsters."]
256    #[inline]
257    pub fn update(self) -> &'a mut W {
258        self.variant(UGW::UPDATE)
259    }
260    #[doc = r" Sets the field bit"]
261    pub fn set_bit(self) -> &'a mut W {
262        self.bit(true)
263    }
264    #[doc = r" Clears the field bit"]
265    pub fn clear_bit(self) -> &'a mut W {
266        self.bit(false)
267    }
268    #[doc = r" Writes raw bits to the field"]
269    #[inline]
270    pub fn bit(self, value: bool) -> &'a mut W {
271        const MASK: bool = true;
272        const OFFSET: u8 = 0;
273        self.w.bits &= !((MASK as u32) << OFFSET);
274        self.w.bits |= ((value & MASK) as u32) << OFFSET;
275        self.w
276    }
277}
278impl W {
279    #[doc = r" Reset value of the register"]
280    #[inline]
281    pub fn reset_value() -> W {
282        W { bits: 0 }
283    }
284    #[doc = r" Writes raw bits to the register"]
285    #[inline]
286    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
287        self.bits = bits;
288        self
289    }
290    #[doc = "Bit 6 - Trigger generation"]
291    #[inline]
292    pub fn tg(&mut self) -> _TGW {
293        _TGW { w: self }
294    }
295    #[doc = "Bit 4 - Capture/compare 4 generation"]
296    #[inline]
297    pub fn cc4g(&mut self) -> _CC4GW {
298        _CC4GW { w: self }
299    }
300    #[doc = "Bit 3 - Capture/compare 3 generation"]
301    #[inline]
302    pub fn cc3g(&mut self) -> _CC3GW {
303        _CC3GW { w: self }
304    }
305    #[doc = "Bit 2 - Capture/compare 2 generation"]
306    #[inline]
307    pub fn cc2g(&mut self) -> _CC2GW {
308        _CC2GW { w: self }
309    }
310    #[doc = "Bit 1 - Capture/compare 1 generation"]
311    #[inline]
312    pub fn cc1g(&mut self) -> _CC1GW {
313        _CC1GW { w: self }
314    }
315    #[doc = "Bit 0 - Update generation"]
316    #[inline]
317    pub fn ug(&mut self) -> _UGW {
318        _UGW { w: self }
319    }
320}
stm32l4x2_pac/tim2/egr.rs

stm32l4x2_pac/tim2/
egr.rs
