1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::CR2 {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = "Possible values of the field `TI1S`"]
46#[derive(Clone, Copy, Debug, PartialEq)]
47pub enum TI1SR {
48 #[doc = "The TIMx_CH1 pin is connected to TI1 input"]
49 NORMAL,
50 #[doc = "The TIMx_CH1, CH2, CH3 pins are connected to TI1 input"]
51 XOR,
52}
53impl TI1SR {
54 #[doc = r" Returns `true` if the bit is clear (0)"]
55 #[inline]
56 pub fn bit_is_clear(&self) -> bool {
57 !self.bit()
58 }
59 #[doc = r" Returns `true` if the bit is set (1)"]
60 #[inline]
61 pub fn bit_is_set(&self) -> bool {
62 self.bit()
63 }
64 #[doc = r" Value of the field as raw bits"]
65 #[inline]
66 pub fn bit(&self) -> bool {
67 match *self {
68 TI1SR::NORMAL => false,
69 TI1SR::XOR => true,
70 }
71 }
72 #[allow(missing_docs)]
73 #[doc(hidden)]
74 #[inline]
75 pub fn _from(value: bool) -> TI1SR {
76 match value {
77 false => TI1SR::NORMAL,
78 true => TI1SR::XOR,
79 }
80 }
81 #[doc = "Checks if the value of the field is `NORMAL`"]
82 #[inline]
83 pub fn is_normal(&self) -> bool {
84 *self == TI1SR::NORMAL
85 }
86 #[doc = "Checks if the value of the field is `XOR`"]
87 #[inline]
88 pub fn is_xor(&self) -> bool {
89 *self == TI1SR::XOR
90 }
91}
92#[doc = "Possible values of the field `MMS`"]
93#[derive(Clone, Copy, Debug, PartialEq)]
94pub enum MMSR {
95 #[doc = "The UG bit from the TIMx_EGR register is used as trigger output"]
96 RESET,
97 #[doc = "The counter enable signal, CNT_EN, is used as trigger output"]
98 ENABLE,
99 #[doc = "The update event is selected as trigger output"]
100 UPDATE,
101 #[doc = "The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred"]
102 COMPAREPULSE,
103 #[doc = "OC1REF signal is used as trigger output"]
104 COMPAREOC1,
105 #[doc = "OC2REF signal is used as trigger output"]
106 COMPAREOC2,
107 #[doc = "OC3REF signal is used as trigger output"]
108 COMPAREOC3,
109 #[doc = "OC4REF signal is used as trigger output"]
110 COMPAREOC4,
111}
112impl MMSR {
113 #[doc = r" Value of the field as raw bits"]
114 #[inline]
115 pub fn bits(&self) -> u8 {
116 match *self {
117 MMSR::RESET => 0,
118 MMSR::ENABLE => 1,
119 MMSR::UPDATE => 2,
120 MMSR::COMPAREPULSE => 3,
121 MMSR::COMPAREOC1 => 4,
122 MMSR::COMPAREOC2 => 5,
123 MMSR::COMPAREOC3 => 6,
124 MMSR::COMPAREOC4 => 7,
125 }
126 }
127 #[allow(missing_docs)]
128 #[doc(hidden)]
129 #[inline]
130 pub fn _from(value: u8) -> MMSR {
131 match value {
132 0 => MMSR::RESET,
133 1 => MMSR::ENABLE,
134 2 => MMSR::UPDATE,
135 3 => MMSR::COMPAREPULSE,
136 4 => MMSR::COMPAREOC1,
137 5 => MMSR::COMPAREOC2,
138 6 => MMSR::COMPAREOC3,
139 7 => MMSR::COMPAREOC4,
140 _ => unreachable!(),
141 }
142 }
143 #[doc = "Checks if the value of the field is `RESET`"]
144 #[inline]
145 pub fn is_reset(&self) -> bool {
146 *self == MMSR::RESET
147 }
148 #[doc = "Checks if the value of the field is `ENABLE`"]
149 #[inline]
150 pub fn is_enable(&self) -> bool {
151 *self == MMSR::ENABLE
152 }
153 #[doc = "Checks if the value of the field is `UPDATE`"]
154 #[inline]
155 pub fn is_update(&self) -> bool {
156 *self == MMSR::UPDATE
157 }
158 #[doc = "Checks if the value of the field is `COMPAREPULSE`"]
159 #[inline]
160 pub fn is_compare_pulse(&self) -> bool {
161 *self == MMSR::COMPAREPULSE
162 }
163 #[doc = "Checks if the value of the field is `COMPAREOC1`"]
164 #[inline]
165 pub fn is_compare_oc1(&self) -> bool {
166 *self == MMSR::COMPAREOC1
167 }
168 #[doc = "Checks if the value of the field is `COMPAREOC2`"]
169 #[inline]
170 pub fn is_compare_oc2(&self) -> bool {
171 *self == MMSR::COMPAREOC2
172 }
173 #[doc = "Checks if the value of the field is `COMPAREOC3`"]
174 #[inline]
175 pub fn is_compare_oc3(&self) -> bool {
176 *self == MMSR::COMPAREOC3
177 }
178 #[doc = "Checks if the value of the field is `COMPAREOC4`"]
179 #[inline]
180 pub fn is_compare_oc4(&self) -> bool {
181 *self == MMSR::COMPAREOC4
182 }
183}
184#[doc = "Possible values of the field `CCDS`"]
185#[derive(Clone, Copy, Debug, PartialEq)]
186pub enum CCDSR {
187 #[doc = "CCx DMA request sent when CCx event occurs"]
188 ONCOMPARE,
189 #[doc = "CCx DMA request sent when update event occurs"]
190 ONUPDATE,
191}
192impl CCDSR {
193 #[doc = r" Returns `true` if the bit is clear (0)"]
194 #[inline]
195 pub fn bit_is_clear(&self) -> bool {
196 !self.bit()
197 }
198 #[doc = r" Returns `true` if the bit is set (1)"]
199 #[inline]
200 pub fn bit_is_set(&self) -> bool {
201 self.bit()
202 }
203 #[doc = r" Value of the field as raw bits"]
204 #[inline]
205 pub fn bit(&self) -> bool {
206 match *self {
207 CCDSR::ONCOMPARE => false,
208 CCDSR::ONUPDATE => true,
209 }
210 }
211 #[allow(missing_docs)]
212 #[doc(hidden)]
213 #[inline]
214 pub fn _from(value: bool) -> CCDSR {
215 match value {
216 false => CCDSR::ONCOMPARE,
217 true => CCDSR::ONUPDATE,
218 }
219 }
220 #[doc = "Checks if the value of the field is `ONCOMPARE`"]
221 #[inline]
222 pub fn is_on_compare(&self) -> bool {
223 *self == CCDSR::ONCOMPARE
224 }
225 #[doc = "Checks if the value of the field is `ONUPDATE`"]
226 #[inline]
227 pub fn is_on_update(&self) -> bool {
228 *self == CCDSR::ONUPDATE
229 }
230}
231#[doc = "Values that can be written to the field `TI1S`"]
232pub enum TI1SW {
233 #[doc = "The TIMx_CH1 pin is connected to TI1 input"]
234 NORMAL,
235 #[doc = "The TIMx_CH1, CH2, CH3 pins are connected to TI1 input"]
236 XOR,
237}
238impl TI1SW {
239 #[allow(missing_docs)]
240 #[doc(hidden)]
241 #[inline]
242 pub fn _bits(&self) -> bool {
243 match *self {
244 TI1SW::NORMAL => false,
245 TI1SW::XOR => true,
246 }
247 }
248}
249#[doc = r" Proxy"]
250pub struct _TI1SW<'a> {
251 w: &'a mut W,
252}
253impl<'a> _TI1SW<'a> {
254 #[doc = r" Writes `variant` to the field"]
255 #[inline]
256 pub fn variant(self, variant: TI1SW) -> &'a mut W {
257 {
258 self.bit(variant._bits())
259 }
260 }
261 #[doc = "The TIMx_CH1 pin is connected to TI1 input"]
262 #[inline]
263 pub fn normal(self) -> &'a mut W {
264 self.variant(TI1SW::NORMAL)
265 }
266 #[doc = "The TIMx_CH1, CH2, CH3 pins are connected to TI1 input"]
267 #[inline]
268 pub fn xor(self) -> &'a mut W {
269 self.variant(TI1SW::XOR)
270 }
271 #[doc = r" Sets the field bit"]
272 pub fn set_bit(self) -> &'a mut W {
273 self.bit(true)
274 }
275 #[doc = r" Clears the field bit"]
276 pub fn clear_bit(self) -> &'a mut W {
277 self.bit(false)
278 }
279 #[doc = r" Writes raw bits to the field"]
280 #[inline]
281 pub fn bit(self, value: bool) -> &'a mut W {
282 const MASK: bool = true;
283 const OFFSET: u8 = 7;
284 self.w.bits &= !((MASK as u32) << OFFSET);
285 self.w.bits |= ((value & MASK) as u32) << OFFSET;
286 self.w
287 }
288}
289#[doc = "Values that can be written to the field `MMS`"]
290pub enum MMSW {
291 #[doc = "The UG bit from the TIMx_EGR register is used as trigger output"]
292 RESET,
293 #[doc = "The counter enable signal, CNT_EN, is used as trigger output"]
294 ENABLE,
295 #[doc = "The update event is selected as trigger output"]
296 UPDATE,
297 #[doc = "The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred"]
298 COMPAREPULSE,
299 #[doc = "OC1REF signal is used as trigger output"]
300 COMPAREOC1,
301 #[doc = "OC2REF signal is used as trigger output"]
302 COMPAREOC2,
303 #[doc = "OC3REF signal is used as trigger output"]
304 COMPAREOC3,
305 #[doc = "OC4REF signal is used as trigger output"]
306 COMPAREOC4,
307}
308impl MMSW {
309 #[allow(missing_docs)]
310 #[doc(hidden)]
311 #[inline]
312 pub fn _bits(&self) -> u8 {
313 match *self {
314 MMSW::RESET => 0,
315 MMSW::ENABLE => 1,
316 MMSW::UPDATE => 2,
317 MMSW::COMPAREPULSE => 3,
318 MMSW::COMPAREOC1 => 4,
319 MMSW::COMPAREOC2 => 5,
320 MMSW::COMPAREOC3 => 6,
321 MMSW::COMPAREOC4 => 7,
322 }
323 }
324}
325#[doc = r" Proxy"]
326pub struct _MMSW<'a> {
327 w: &'a mut W,
328}
329impl<'a> _MMSW<'a> {
330 #[doc = r" Writes `variant` to the field"]
331 #[inline]
332 pub fn variant(self, variant: MMSW) -> &'a mut W {
333 {
334 self.bits(variant._bits())
335 }
336 }
337 #[doc = "The UG bit from the TIMx_EGR register is used as trigger output"]
338 #[inline]
339 pub fn reset(self) -> &'a mut W {
340 self.variant(MMSW::RESET)
341 }
342 #[doc = "The counter enable signal, CNT_EN, is used as trigger output"]
343 #[inline]
344 pub fn enable(self) -> &'a mut W {
345 self.variant(MMSW::ENABLE)
346 }
347 #[doc = "The update event is selected as trigger output"]
348 #[inline]
349 pub fn update(self) -> &'a mut W {
350 self.variant(MMSW::UPDATE)
351 }
352 #[doc = "The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred"]
353 #[inline]
354 pub fn compare_pulse(self) -> &'a mut W {
355 self.variant(MMSW::COMPAREPULSE)
356 }
357 #[doc = "OC1REF signal is used as trigger output"]
358 #[inline]
359 pub fn compare_oc1(self) -> &'a mut W {
360 self.variant(MMSW::COMPAREOC1)
361 }
362 #[doc = "OC2REF signal is used as trigger output"]
363 #[inline]
364 pub fn compare_oc2(self) -> &'a mut W {
365 self.variant(MMSW::COMPAREOC2)
366 }
367 #[doc = "OC3REF signal is used as trigger output"]
368 #[inline]
369 pub fn compare_oc3(self) -> &'a mut W {
370 self.variant(MMSW::COMPAREOC3)
371 }
372 #[doc = "OC4REF signal is used as trigger output"]
373 #[inline]
374 pub fn compare_oc4(self) -> &'a mut W {
375 self.variant(MMSW::COMPAREOC4)
376 }
377 #[doc = r" Writes raw bits to the field"]
378 #[inline]
379 pub fn bits(self, value: u8) -> &'a mut W {
380 const MASK: u8 = 7;
381 const OFFSET: u8 = 4;
382 self.w.bits &= !((MASK as u32) << OFFSET);
383 self.w.bits |= ((value & MASK) as u32) << OFFSET;
384 self.w
385 }
386}
387#[doc = "Values that can be written to the field `CCDS`"]
388pub enum CCDSW {
389 #[doc = "CCx DMA request sent when CCx event occurs"]
390 ONCOMPARE,
391 #[doc = "CCx DMA request sent when update event occurs"]
392 ONUPDATE,
393}
394impl CCDSW {
395 #[allow(missing_docs)]
396 #[doc(hidden)]
397 #[inline]
398 pub fn _bits(&self) -> bool {
399 match *self {
400 CCDSW::ONCOMPARE => false,
401 CCDSW::ONUPDATE => true,
402 }
403 }
404}
405#[doc = r" Proxy"]
406pub struct _CCDSW<'a> {
407 w: &'a mut W,
408}
409impl<'a> _CCDSW<'a> {
410 #[doc = r" Writes `variant` to the field"]
411 #[inline]
412 pub fn variant(self, variant: CCDSW) -> &'a mut W {
413 {
414 self.bit(variant._bits())
415 }
416 }
417 #[doc = "CCx DMA request sent when CCx event occurs"]
418 #[inline]
419 pub fn on_compare(self) -> &'a mut W {
420 self.variant(CCDSW::ONCOMPARE)
421 }
422 #[doc = "CCx DMA request sent when update event occurs"]
423 #[inline]
424 pub fn on_update(self) -> &'a mut W {
425 self.variant(CCDSW::ONUPDATE)
426 }
427 #[doc = r" Sets the field bit"]
428 pub fn set_bit(self) -> &'a mut W {
429 self.bit(true)
430 }
431 #[doc = r" Clears the field bit"]
432 pub fn clear_bit(self) -> &'a mut W {
433 self.bit(false)
434 }
435 #[doc = r" Writes raw bits to the field"]
436 #[inline]
437 pub fn bit(self, value: bool) -> &'a mut W {
438 const MASK: bool = true;
439 const OFFSET: u8 = 3;
440 self.w.bits &= !((MASK as u32) << OFFSET);
441 self.w.bits |= ((value & MASK) as u32) << OFFSET;
442 self.w
443 }
444}
445impl R {
446 #[doc = r" Value of the register as raw bits"]
447 #[inline]
448 pub fn bits(&self) -> u32 {
449 self.bits
450 }
451 #[doc = "Bit 7 - TI1 selection"]
452 #[inline]
453 pub fn ti1s(&self) -> TI1SR {
454 TI1SR::_from({
455 const MASK: bool = true;
456 const OFFSET: u8 = 7;
457 ((self.bits >> OFFSET) & MASK as u32) != 0
458 })
459 }
460 #[doc = "Bits 4:6 - Master mode selection"]
461 #[inline]
462 pub fn mms(&self) -> MMSR {
463 MMSR::_from({
464 const MASK: u8 = 7;
465 const OFFSET: u8 = 4;
466 ((self.bits >> OFFSET) & MASK as u32) as u8
467 })
468 }
469 #[doc = "Bit 3 - Capture/compare DMA selection"]
470 #[inline]
471 pub fn ccds(&self) -> CCDSR {
472 CCDSR::_from({
473 const MASK: bool = true;
474 const OFFSET: u8 = 3;
475 ((self.bits >> OFFSET) & MASK as u32) != 0
476 })
477 }
478}
479impl W {
480 #[doc = r" Reset value of the register"]
481 #[inline]
482 pub fn reset_value() -> W {
483 W { bits: 0 }
484 }
485 #[doc = r" Writes raw bits to the register"]
486 #[inline]
487 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
488 self.bits = bits;
489 self
490 }
491 #[doc = "Bit 7 - TI1 selection"]
492 #[inline]
493 pub fn ti1s(&mut self) -> _TI1SW {
494 _TI1SW { w: self }
495 }
496 #[doc = "Bits 4:6 - Master mode selection"]
497 #[inline]
498 pub fn mms(&mut self) -> _MMSW {
499 _MMSW { w: self }
500 }
501 #[doc = "Bit 3 - Capture/compare DMA selection"]
502 #[inline]
503 pub fn ccds(&mut self) -> _CCDSW {
504 _CCDSW { w: self }
505 }
506}