1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::CR1 {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = "Possible values of the field `CKD`"]
46#[derive(Clone, Copy, Debug, PartialEq)]
47pub enum CKDR {
48 #[doc = "CK_INT not divided"]
49 NOTDIVIDED,
50 #[doc = "CK_INT divided by 2"]
51 DIVIDEDBY2,
52 #[doc = "CK_INT divided by 4"]
53 DIVIDEDBY4,
54 #[doc = r" Reserved"]
55 _Reserved(u8),
56}
57impl CKDR {
58 #[doc = r" Value of the field as raw bits"]
59 #[inline]
60 pub fn bits(&self) -> u8 {
61 match *self {
62 CKDR::NOTDIVIDED => 0,
63 CKDR::DIVIDEDBY2 => 1,
64 CKDR::DIVIDEDBY4 => 2,
65 CKDR::_Reserved(bits) => bits,
66 }
67 }
68 #[allow(missing_docs)]
69 #[doc(hidden)]
70 #[inline]
71 pub fn _from(value: u8) -> CKDR {
72 match value {
73 0 => CKDR::NOTDIVIDED,
74 1 => CKDR::DIVIDEDBY2,
75 2 => CKDR::DIVIDEDBY4,
76 i => CKDR::_Reserved(i),
77 }
78 }
79 #[doc = "Checks if the value of the field is `NOTDIVIDED`"]
80 #[inline]
81 pub fn is_not_divided(&self) -> bool {
82 *self == CKDR::NOTDIVIDED
83 }
84 #[doc = "Checks if the value of the field is `DIVIDEDBY2`"]
85 #[inline]
86 pub fn is_divided_by2(&self) -> bool {
87 *self == CKDR::DIVIDEDBY2
88 }
89 #[doc = "Checks if the value of the field is `DIVIDEDBY4`"]
90 #[inline]
91 pub fn is_divided_by4(&self) -> bool {
92 *self == CKDR::DIVIDEDBY4
93 }
94}
95#[doc = "Possible values of the field `ARPE`"]
96#[derive(Clone, Copy, Debug, PartialEq)]
97pub enum ARPER {
98 #[doc = "TIMx_APRR register is not buffered"]
99 DISABLED,
100 #[doc = "TIMx_APRR register is buffered"]
101 ENABLED,
102}
103impl ARPER {
104 #[doc = r" Returns `true` if the bit is clear (0)"]
105 #[inline]
106 pub fn bit_is_clear(&self) -> bool {
107 !self.bit()
108 }
109 #[doc = r" Returns `true` if the bit is set (1)"]
110 #[inline]
111 pub fn bit_is_set(&self) -> bool {
112 self.bit()
113 }
114 #[doc = r" Value of the field as raw bits"]
115 #[inline]
116 pub fn bit(&self) -> bool {
117 match *self {
118 ARPER::DISABLED => false,
119 ARPER::ENABLED => true,
120 }
121 }
122 #[allow(missing_docs)]
123 #[doc(hidden)]
124 #[inline]
125 pub fn _from(value: bool) -> ARPER {
126 match value {
127 false => ARPER::DISABLED,
128 true => ARPER::ENABLED,
129 }
130 }
131 #[doc = "Checks if the value of the field is `DISABLED`"]
132 #[inline]
133 pub fn is_disabled(&self) -> bool {
134 *self == ARPER::DISABLED
135 }
136 #[doc = "Checks if the value of the field is `ENABLED`"]
137 #[inline]
138 pub fn is_enabled(&self) -> bool {
139 *self == ARPER::ENABLED
140 }
141}
142#[doc = r" Value of the field"]
143pub struct CMSR {
144 bits: u8,
145}
146impl CMSR {
147 #[doc = r" Value of the field as raw bits"]
148 #[inline]
149 pub fn bits(&self) -> u8 {
150 self.bits
151 }
152}
153#[doc = r" Value of the field"]
154pub struct DIRR {
155 bits: bool,
156}
157impl DIRR {
158 #[doc = r" Value of the field as raw bits"]
159 #[inline]
160 pub fn bit(&self) -> bool {
161 self.bits
162 }
163 #[doc = r" Returns `true` if the bit is clear (0)"]
164 #[inline]
165 pub fn bit_is_clear(&self) -> bool {
166 !self.bit()
167 }
168 #[doc = r" Returns `true` if the bit is set (1)"]
169 #[inline]
170 pub fn bit_is_set(&self) -> bool {
171 self.bit()
172 }
173}
174#[doc = "Possible values of the field `OPM`"]
175#[derive(Clone, Copy, Debug, PartialEq)]
176pub enum OPMR {
177 #[doc = "Counter is not stopped at update event"]
178 DISABLED,
179 #[doc = "Counter stops counting at the next update event (clearing the CEN bit)"]
180 ENABLED,
181}
182impl OPMR {
183 #[doc = r" Returns `true` if the bit is clear (0)"]
184 #[inline]
185 pub fn bit_is_clear(&self) -> bool {
186 !self.bit()
187 }
188 #[doc = r" Returns `true` if the bit is set (1)"]
189 #[inline]
190 pub fn bit_is_set(&self) -> bool {
191 self.bit()
192 }
193 #[doc = r" Value of the field as raw bits"]
194 #[inline]
195 pub fn bit(&self) -> bool {
196 match *self {
197 OPMR::DISABLED => false,
198 OPMR::ENABLED => true,
199 }
200 }
201 #[allow(missing_docs)]
202 #[doc(hidden)]
203 #[inline]
204 pub fn _from(value: bool) -> OPMR {
205 match value {
206 false => OPMR::DISABLED,
207 true => OPMR::ENABLED,
208 }
209 }
210 #[doc = "Checks if the value of the field is `DISABLED`"]
211 #[inline]
212 pub fn is_disabled(&self) -> bool {
213 *self == OPMR::DISABLED
214 }
215 #[doc = "Checks if the value of the field is `ENABLED`"]
216 #[inline]
217 pub fn is_enabled(&self) -> bool {
218 *self == OPMR::ENABLED
219 }
220}
221#[doc = "Possible values of the field `URS`"]
222#[derive(Clone, Copy, Debug, PartialEq)]
223pub enum URSR {
224 #[doc = "Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request"]
225 ANYEVENT,
226 #[doc = "Only counter overflow/underflow generates an update interrupt or DMA request"]
227 COUNTERONLY,
228}
229impl URSR {
230 #[doc = r" Returns `true` if the bit is clear (0)"]
231 #[inline]
232 pub fn bit_is_clear(&self) -> bool {
233 !self.bit()
234 }
235 #[doc = r" Returns `true` if the bit is set (1)"]
236 #[inline]
237 pub fn bit_is_set(&self) -> bool {
238 self.bit()
239 }
240 #[doc = r" Value of the field as raw bits"]
241 #[inline]
242 pub fn bit(&self) -> bool {
243 match *self {
244 URSR::ANYEVENT => false,
245 URSR::COUNTERONLY => true,
246 }
247 }
248 #[allow(missing_docs)]
249 #[doc(hidden)]
250 #[inline]
251 pub fn _from(value: bool) -> URSR {
252 match value {
253 false => URSR::ANYEVENT,
254 true => URSR::COUNTERONLY,
255 }
256 }
257 #[doc = "Checks if the value of the field is `ANYEVENT`"]
258 #[inline]
259 pub fn is_any_event(&self) -> bool {
260 *self == URSR::ANYEVENT
261 }
262 #[doc = "Checks if the value of the field is `COUNTERONLY`"]
263 #[inline]
264 pub fn is_counter_only(&self) -> bool {
265 *self == URSR::COUNTERONLY
266 }
267}
268#[doc = "Possible values of the field `UDIS`"]
269#[derive(Clone, Copy, Debug, PartialEq)]
270pub enum UDISR {
271 #[doc = "Update event enabled"]
272 ENABLED,
273 #[doc = "Update event disabled"]
274 DISABLED,
275}
276impl UDISR {
277 #[doc = r" Returns `true` if the bit is clear (0)"]
278 #[inline]
279 pub fn bit_is_clear(&self) -> bool {
280 !self.bit()
281 }
282 #[doc = r" Returns `true` if the bit is set (1)"]
283 #[inline]
284 pub fn bit_is_set(&self) -> bool {
285 self.bit()
286 }
287 #[doc = r" Value of the field as raw bits"]
288 #[inline]
289 pub fn bit(&self) -> bool {
290 match *self {
291 UDISR::ENABLED => false,
292 UDISR::DISABLED => true,
293 }
294 }
295 #[allow(missing_docs)]
296 #[doc(hidden)]
297 #[inline]
298 pub fn _from(value: bool) -> UDISR {
299 match value {
300 false => UDISR::ENABLED,
301 true => UDISR::DISABLED,
302 }
303 }
304 #[doc = "Checks if the value of the field is `ENABLED`"]
305 #[inline]
306 pub fn is_enabled(&self) -> bool {
307 *self == UDISR::ENABLED
308 }
309 #[doc = "Checks if the value of the field is `DISABLED`"]
310 #[inline]
311 pub fn is_disabled(&self) -> bool {
312 *self == UDISR::DISABLED
313 }
314}
315#[doc = "Possible values of the field `CEN`"]
316#[derive(Clone, Copy, Debug, PartialEq)]
317pub enum CENR {
318 #[doc = "Counter disabled"]
319 DISABLED,
320 #[doc = "Counter enabled"]
321 ENABLED,
322}
323impl CENR {
324 #[doc = r" Returns `true` if the bit is clear (0)"]
325 #[inline]
326 pub fn bit_is_clear(&self) -> bool {
327 !self.bit()
328 }
329 #[doc = r" Returns `true` if the bit is set (1)"]
330 #[inline]
331 pub fn bit_is_set(&self) -> bool {
332 self.bit()
333 }
334 #[doc = r" Value of the field as raw bits"]
335 #[inline]
336 pub fn bit(&self) -> bool {
337 match *self {
338 CENR::DISABLED => false,
339 CENR::ENABLED => true,
340 }
341 }
342 #[allow(missing_docs)]
343 #[doc(hidden)]
344 #[inline]
345 pub fn _from(value: bool) -> CENR {
346 match value {
347 false => CENR::DISABLED,
348 true => CENR::ENABLED,
349 }
350 }
351 #[doc = "Checks if the value of the field is `DISABLED`"]
352 #[inline]
353 pub fn is_disabled(&self) -> bool {
354 *self == CENR::DISABLED
355 }
356 #[doc = "Checks if the value of the field is `ENABLED`"]
357 #[inline]
358 pub fn is_enabled(&self) -> bool {
359 *self == CENR::ENABLED
360 }
361}
362#[doc = "Values that can be written to the field `CKD`"]
363pub enum CKDW {
364 #[doc = "CK_INT not divided"]
365 NOTDIVIDED,
366 #[doc = "CK_INT divided by 2"]
367 DIVIDEDBY2,
368 #[doc = "CK_INT divided by 4"]
369 DIVIDEDBY4,
370}
371impl CKDW {
372 #[allow(missing_docs)]
373 #[doc(hidden)]
374 #[inline]
375 pub fn _bits(&self) -> u8 {
376 match *self {
377 CKDW::NOTDIVIDED => 0,
378 CKDW::DIVIDEDBY2 => 1,
379 CKDW::DIVIDEDBY4 => 2,
380 }
381 }
382}
383#[doc = r" Proxy"]
384pub struct _CKDW<'a> {
385 w: &'a mut W,
386}
387impl<'a> _CKDW<'a> {
388 #[doc = r" Writes `variant` to the field"]
389 #[inline]
390 pub fn variant(self, variant: CKDW) -> &'a mut W {
391 unsafe { self.bits(variant._bits()) }
392 }
393 #[doc = "CK_INT not divided"]
394 #[inline]
395 pub fn not_divided(self) -> &'a mut W {
396 self.variant(CKDW::NOTDIVIDED)
397 }
398 #[doc = "CK_INT divided by 2"]
399 #[inline]
400 pub fn divided_by2(self) -> &'a mut W {
401 self.variant(CKDW::DIVIDEDBY2)
402 }
403 #[doc = "CK_INT divided by 4"]
404 #[inline]
405 pub fn divided_by4(self) -> &'a mut W {
406 self.variant(CKDW::DIVIDEDBY4)
407 }
408 #[doc = r" Writes raw bits to the field"]
409 #[inline]
410 pub unsafe fn bits(self, value: u8) -> &'a mut W {
411 const MASK: u8 = 3;
412 const OFFSET: u8 = 8;
413 self.w.bits &= !((MASK as u32) << OFFSET);
414 self.w.bits |= ((value & MASK) as u32) << OFFSET;
415 self.w
416 }
417}
418#[doc = "Values that can be written to the field `ARPE`"]
419pub enum ARPEW {
420 #[doc = "TIMx_APRR register is not buffered"]
421 DISABLED,
422 #[doc = "TIMx_APRR register is buffered"]
423 ENABLED,
424}
425impl ARPEW {
426 #[allow(missing_docs)]
427 #[doc(hidden)]
428 #[inline]
429 pub fn _bits(&self) -> bool {
430 match *self {
431 ARPEW::DISABLED => false,
432 ARPEW::ENABLED => true,
433 }
434 }
435}
436#[doc = r" Proxy"]
437pub struct _ARPEW<'a> {
438 w: &'a mut W,
439}
440impl<'a> _ARPEW<'a> {
441 #[doc = r" Writes `variant` to the field"]
442 #[inline]
443 pub fn variant(self, variant: ARPEW) -> &'a mut W {
444 {
445 self.bit(variant._bits())
446 }
447 }
448 #[doc = "TIMx_APRR register is not buffered"]
449 #[inline]
450 pub fn disabled(self) -> &'a mut W {
451 self.variant(ARPEW::DISABLED)
452 }
453 #[doc = "TIMx_APRR register is buffered"]
454 #[inline]
455 pub fn enabled(self) -> &'a mut W {
456 self.variant(ARPEW::ENABLED)
457 }
458 #[doc = r" Sets the field bit"]
459 pub fn set_bit(self) -> &'a mut W {
460 self.bit(true)
461 }
462 #[doc = r" Clears the field bit"]
463 pub fn clear_bit(self) -> &'a mut W {
464 self.bit(false)
465 }
466 #[doc = r" Writes raw bits to the field"]
467 #[inline]
468 pub fn bit(self, value: bool) -> &'a mut W {
469 const MASK: bool = true;
470 const OFFSET: u8 = 7;
471 self.w.bits &= !((MASK as u32) << OFFSET);
472 self.w.bits |= ((value & MASK) as u32) << OFFSET;
473 self.w
474 }
475}
476#[doc = r" Proxy"]
477pub struct _CMSW<'a> {
478 w: &'a mut W,
479}
480impl<'a> _CMSW<'a> {
481 #[doc = r" Writes raw bits to the field"]
482 #[inline]
483 pub unsafe fn bits(self, value: u8) -> &'a mut W {
484 const MASK: u8 = 3;
485 const OFFSET: u8 = 5;
486 self.w.bits &= !((MASK as u32) << OFFSET);
487 self.w.bits |= ((value & MASK) as u32) << OFFSET;
488 self.w
489 }
490}
491#[doc = r" Proxy"]
492pub struct _DIRW<'a> {
493 w: &'a mut W,
494}
495impl<'a> _DIRW<'a> {
496 #[doc = r" Sets the field bit"]
497 pub fn set_bit(self) -> &'a mut W {
498 self.bit(true)
499 }
500 #[doc = r" Clears the field bit"]
501 pub fn clear_bit(self) -> &'a mut W {
502 self.bit(false)
503 }
504 #[doc = r" Writes raw bits to the field"]
505 #[inline]
506 pub fn bit(self, value: bool) -> &'a mut W {
507 const MASK: bool = true;
508 const OFFSET: u8 = 4;
509 self.w.bits &= !((MASK as u32) << OFFSET);
510 self.w.bits |= ((value & MASK) as u32) << OFFSET;
511 self.w
512 }
513}
514#[doc = "Values that can be written to the field `OPM`"]
515pub enum OPMW {
516 #[doc = "Counter is not stopped at update event"]
517 DISABLED,
518 #[doc = "Counter stops counting at the next update event (clearing the CEN bit)"]
519 ENABLED,
520}
521impl OPMW {
522 #[allow(missing_docs)]
523 #[doc(hidden)]
524 #[inline]
525 pub fn _bits(&self) -> bool {
526 match *self {
527 OPMW::DISABLED => false,
528 OPMW::ENABLED => true,
529 }
530 }
531}
532#[doc = r" Proxy"]
533pub struct _OPMW<'a> {
534 w: &'a mut W,
535}
536impl<'a> _OPMW<'a> {
537 #[doc = r" Writes `variant` to the field"]
538 #[inline]
539 pub fn variant(self, variant: OPMW) -> &'a mut W {
540 {
541 self.bit(variant._bits())
542 }
543 }
544 #[doc = "Counter is not stopped at update event"]
545 #[inline]
546 pub fn disabled(self) -> &'a mut W {
547 self.variant(OPMW::DISABLED)
548 }
549 #[doc = "Counter stops counting at the next update event (clearing the CEN bit)"]
550 #[inline]
551 pub fn enabled(self) -> &'a mut W {
552 self.variant(OPMW::ENABLED)
553 }
554 #[doc = r" Sets the field bit"]
555 pub fn set_bit(self) -> &'a mut W {
556 self.bit(true)
557 }
558 #[doc = r" Clears the field bit"]
559 pub fn clear_bit(self) -> &'a mut W {
560 self.bit(false)
561 }
562 #[doc = r" Writes raw bits to the field"]
563 #[inline]
564 pub fn bit(self, value: bool) -> &'a mut W {
565 const MASK: bool = true;
566 const OFFSET: u8 = 3;
567 self.w.bits &= !((MASK as u32) << OFFSET);
568 self.w.bits |= ((value & MASK) as u32) << OFFSET;
569 self.w
570 }
571}
572#[doc = "Values that can be written to the field `URS`"]
573pub enum URSW {
574 #[doc = "Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request"]
575 ANYEVENT,
576 #[doc = "Only counter overflow/underflow generates an update interrupt or DMA request"]
577 COUNTERONLY,
578}
579impl URSW {
580 #[allow(missing_docs)]
581 #[doc(hidden)]
582 #[inline]
583 pub fn _bits(&self) -> bool {
584 match *self {
585 URSW::ANYEVENT => false,
586 URSW::COUNTERONLY => true,
587 }
588 }
589}
590#[doc = r" Proxy"]
591pub struct _URSW<'a> {
592 w: &'a mut W,
593}
594impl<'a> _URSW<'a> {
595 #[doc = r" Writes `variant` to the field"]
596 #[inline]
597 pub fn variant(self, variant: URSW) -> &'a mut W {
598 {
599 self.bit(variant._bits())
600 }
601 }
602 #[doc = "Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request"]
603 #[inline]
604 pub fn any_event(self) -> &'a mut W {
605 self.variant(URSW::ANYEVENT)
606 }
607 #[doc = "Only counter overflow/underflow generates an update interrupt or DMA request"]
608 #[inline]
609 pub fn counter_only(self) -> &'a mut W {
610 self.variant(URSW::COUNTERONLY)
611 }
612 #[doc = r" Sets the field bit"]
613 pub fn set_bit(self) -> &'a mut W {
614 self.bit(true)
615 }
616 #[doc = r" Clears the field bit"]
617 pub fn clear_bit(self) -> &'a mut W {
618 self.bit(false)
619 }
620 #[doc = r" Writes raw bits to the field"]
621 #[inline]
622 pub fn bit(self, value: bool) -> &'a mut W {
623 const MASK: bool = true;
624 const OFFSET: u8 = 2;
625 self.w.bits &= !((MASK as u32) << OFFSET);
626 self.w.bits |= ((value & MASK) as u32) << OFFSET;
627 self.w
628 }
629}
630#[doc = "Values that can be written to the field `UDIS`"]
631pub enum UDISW {
632 #[doc = "Update event enabled"]
633 ENABLED,
634 #[doc = "Update event disabled"]
635 DISABLED,
636}
637impl UDISW {
638 #[allow(missing_docs)]
639 #[doc(hidden)]
640 #[inline]
641 pub fn _bits(&self) -> bool {
642 match *self {
643 UDISW::ENABLED => false,
644 UDISW::DISABLED => true,
645 }
646 }
647}
648#[doc = r" Proxy"]
649pub struct _UDISW<'a> {
650 w: &'a mut W,
651}
652impl<'a> _UDISW<'a> {
653 #[doc = r" Writes `variant` to the field"]
654 #[inline]
655 pub fn variant(self, variant: UDISW) -> &'a mut W {
656 {
657 self.bit(variant._bits())
658 }
659 }
660 #[doc = "Update event enabled"]
661 #[inline]
662 pub fn enabled(self) -> &'a mut W {
663 self.variant(UDISW::ENABLED)
664 }
665 #[doc = "Update event disabled"]
666 #[inline]
667 pub fn disabled(self) -> &'a mut W {
668 self.variant(UDISW::DISABLED)
669 }
670 #[doc = r" Sets the field bit"]
671 pub fn set_bit(self) -> &'a mut W {
672 self.bit(true)
673 }
674 #[doc = r" Clears the field bit"]
675 pub fn clear_bit(self) -> &'a mut W {
676 self.bit(false)
677 }
678 #[doc = r" Writes raw bits to the field"]
679 #[inline]
680 pub fn bit(self, value: bool) -> &'a mut W {
681 const MASK: bool = true;
682 const OFFSET: u8 = 1;
683 self.w.bits &= !((MASK as u32) << OFFSET);
684 self.w.bits |= ((value & MASK) as u32) << OFFSET;
685 self.w
686 }
687}
688#[doc = "Values that can be written to the field `CEN`"]
689pub enum CENW {
690 #[doc = "Counter disabled"]
691 DISABLED,
692 #[doc = "Counter enabled"]
693 ENABLED,
694}
695impl CENW {
696 #[allow(missing_docs)]
697 #[doc(hidden)]
698 #[inline]
699 pub fn _bits(&self) -> bool {
700 match *self {
701 CENW::DISABLED => false,
702 CENW::ENABLED => true,
703 }
704 }
705}
706#[doc = r" Proxy"]
707pub struct _CENW<'a> {
708 w: &'a mut W,
709}
710impl<'a> _CENW<'a> {
711 #[doc = r" Writes `variant` to the field"]
712 #[inline]
713 pub fn variant(self, variant: CENW) -> &'a mut W {
714 {
715 self.bit(variant._bits())
716 }
717 }
718 #[doc = "Counter disabled"]
719 #[inline]
720 pub fn disabled(self) -> &'a mut W {
721 self.variant(CENW::DISABLED)
722 }
723 #[doc = "Counter enabled"]
724 #[inline]
725 pub fn enabled(self) -> &'a mut W {
726 self.variant(CENW::ENABLED)
727 }
728 #[doc = r" Sets the field bit"]
729 pub fn set_bit(self) -> &'a mut W {
730 self.bit(true)
731 }
732 #[doc = r" Clears the field bit"]
733 pub fn clear_bit(self) -> &'a mut W {
734 self.bit(false)
735 }
736 #[doc = r" Writes raw bits to the field"]
737 #[inline]
738 pub fn bit(self, value: bool) -> &'a mut W {
739 const MASK: bool = true;
740 const OFFSET: u8 = 0;
741 self.w.bits &= !((MASK as u32) << OFFSET);
742 self.w.bits |= ((value & MASK) as u32) << OFFSET;
743 self.w
744 }
745}
746impl R {
747 #[doc = r" Value of the register as raw bits"]
748 #[inline]
749 pub fn bits(&self) -> u32 {
750 self.bits
751 }
752 #[doc = "Bits 8:9 - Clock division"]
753 #[inline]
754 pub fn ckd(&self) -> CKDR {
755 CKDR::_from({
756 const MASK: u8 = 3;
757 const OFFSET: u8 = 8;
758 ((self.bits >> OFFSET) & MASK as u32) as u8
759 })
760 }
761 #[doc = "Bit 7 - Auto-reload preload enable"]
762 #[inline]
763 pub fn arpe(&self) -> ARPER {
764 ARPER::_from({
765 const MASK: bool = true;
766 const OFFSET: u8 = 7;
767 ((self.bits >> OFFSET) & MASK as u32) != 0
768 })
769 }
770 #[doc = "Bits 5:6 - Center-aligned mode selection"]
771 #[inline]
772 pub fn cms(&self) -> CMSR {
773 let bits = {
774 const MASK: u8 = 3;
775 const OFFSET: u8 = 5;
776 ((self.bits >> OFFSET) & MASK as u32) as u8
777 };
778 CMSR { bits }
779 }
780 #[doc = "Bit 4 - Direction"]
781 #[inline]
782 pub fn dir(&self) -> DIRR {
783 let bits = {
784 const MASK: bool = true;
785 const OFFSET: u8 = 4;
786 ((self.bits >> OFFSET) & MASK as u32) != 0
787 };
788 DIRR { bits }
789 }
790 #[doc = "Bit 3 - One-pulse mode"]
791 #[inline]
792 pub fn opm(&self) -> OPMR {
793 OPMR::_from({
794 const MASK: bool = true;
795 const OFFSET: u8 = 3;
796 ((self.bits >> OFFSET) & MASK as u32) != 0
797 })
798 }
799 #[doc = "Bit 2 - Update request source"]
800 #[inline]
801 pub fn urs(&self) -> URSR {
802 URSR::_from({
803 const MASK: bool = true;
804 const OFFSET: u8 = 2;
805 ((self.bits >> OFFSET) & MASK as u32) != 0
806 })
807 }
808 #[doc = "Bit 1 - Update disable"]
809 #[inline]
810 pub fn udis(&self) -> UDISR {
811 UDISR::_from({
812 const MASK: bool = true;
813 const OFFSET: u8 = 1;
814 ((self.bits >> OFFSET) & MASK as u32) != 0
815 })
816 }
817 #[doc = "Bit 0 - Counter enable"]
818 #[inline]
819 pub fn cen(&self) -> CENR {
820 CENR::_from({
821 const MASK: bool = true;
822 const OFFSET: u8 = 0;
823 ((self.bits >> OFFSET) & MASK as u32) != 0
824 })
825 }
826}
827impl W {
828 #[doc = r" Reset value of the register"]
829 #[inline]
830 pub fn reset_value() -> W {
831 W { bits: 0 }
832 }
833 #[doc = r" Writes raw bits to the register"]
834 #[inline]
835 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
836 self.bits = bits;
837 self
838 }
839 #[doc = "Bits 8:9 - Clock division"]
840 #[inline]
841 pub fn ckd(&mut self) -> _CKDW {
842 _CKDW { w: self }
843 }
844 #[doc = "Bit 7 - Auto-reload preload enable"]
845 #[inline]
846 pub fn arpe(&mut self) -> _ARPEW {
847 _ARPEW { w: self }
848 }
849 #[doc = "Bits 5:6 - Center-aligned mode selection"]
850 #[inline]
851 pub fn cms(&mut self) -> _CMSW {
852 _CMSW { w: self }
853 }
854 #[doc = "Bit 4 - Direction"]
855 #[inline]
856 pub fn dir(&mut self) -> _DIRW {
857 _DIRW { w: self }
858 }
859 #[doc = "Bit 3 - One-pulse mode"]
860 #[inline]
861 pub fn opm(&mut self) -> _OPMW {
862 _OPMW { w: self }
863 }
864 #[doc = "Bit 2 - Update request source"]
865 #[inline]
866 pub fn urs(&mut self) -> _URSW {
867 _URSW { w: self }
868 }
869 #[doc = "Bit 1 - Update disable"]
870 #[inline]
871 pub fn udis(&mut self) -> _UDISW {
872 _UDISW { w: self }
873 }
874 #[doc = "Bit 0 - Counter enable"]
875 #[inline]
876 pub fn cen(&mut self) -> _CENW {
877 _CENW { w: self }
878 }
879}