1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::CCMR2_INPUT {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = r" Value of the field"]
46pub struct IC4FR {
47 bits: u8,
48}
49impl IC4FR {
50 #[doc = r" Value of the field as raw bits"]
51 #[inline]
52 pub fn bits(&self) -> u8 {
53 self.bits
54 }
55}
56#[doc = r" Value of the field"]
57pub struct IC4PSCR {
58 bits: u8,
59}
60impl IC4PSCR {
61 #[doc = r" Value of the field as raw bits"]
62 #[inline]
63 pub fn bits(&self) -> u8 {
64 self.bits
65 }
66}
67#[doc = "Possible values of the field `CC4S`"]
68#[derive(Clone, Copy, Debug, PartialEq)]
69pub enum CC4SR {
70 #[doc = "CC4 channel is configured as output"]
71 OUTPUT,
72 #[doc = "CC4 channel is configured as input, IC4 is mapped on TI4"]
73 TI4,
74 #[doc = "CC4 channel is configured as input, IC4 is mapped on TI3"]
75 TI3,
76 #[doc = "CC4 channel is configured as input, IC4 is mapped on TRC"]
77 TRC,
78}
79impl CC4SR {
80 #[doc = r" Value of the field as raw bits"]
81 #[inline]
82 pub fn bits(&self) -> u8 {
83 match *self {
84 CC4SR::OUTPUT => 0,
85 CC4SR::TI4 => 1,
86 CC4SR::TI3 => 2,
87 CC4SR::TRC => 3,
88 }
89 }
90 #[allow(missing_docs)]
91 #[doc(hidden)]
92 #[inline]
93 pub fn _from(value: u8) -> CC4SR {
94 match value {
95 0 => CC4SR::OUTPUT,
96 1 => CC4SR::TI4,
97 2 => CC4SR::TI3,
98 3 => CC4SR::TRC,
99 _ => unreachable!(),
100 }
101 }
102 #[doc = "Checks if the value of the field is `OUTPUT`"]
103 #[inline]
104 pub fn is_output(&self) -> bool {
105 *self == CC4SR::OUTPUT
106 }
107 #[doc = "Checks if the value of the field is `TI4`"]
108 #[inline]
109 pub fn is_ti4(&self) -> bool {
110 *self == CC4SR::TI4
111 }
112 #[doc = "Checks if the value of the field is `TI3`"]
113 #[inline]
114 pub fn is_ti3(&self) -> bool {
115 *self == CC4SR::TI3
116 }
117 #[doc = "Checks if the value of the field is `TRC`"]
118 #[inline]
119 pub fn is_trc(&self) -> bool {
120 *self == CC4SR::TRC
121 }
122}
123#[doc = r" Value of the field"]
124pub struct IC3FR {
125 bits: u8,
126}
127impl IC3FR {
128 #[doc = r" Value of the field as raw bits"]
129 #[inline]
130 pub fn bits(&self) -> u8 {
131 self.bits
132 }
133}
134#[doc = r" Value of the field"]
135pub struct IC3PSCR {
136 bits: u8,
137}
138impl IC3PSCR {
139 #[doc = r" Value of the field as raw bits"]
140 #[inline]
141 pub fn bits(&self) -> u8 {
142 self.bits
143 }
144}
145#[doc = "Possible values of the field `CC3S`"]
146#[derive(Clone, Copy, Debug, PartialEq)]
147pub enum CC3SR {
148 #[doc = "CC3 channel is configured as output"]
149 OUTPUT,
150 #[doc = "CC3 channel is configured as input, IC3 is mapped on TI3"]
151 TI3,
152 #[doc = "CC3 channel is configured as input, IC3 is mapped on TI4"]
153 TI4,
154 #[doc = "CC3 channel is configured as input, IC3 is mapped on TRC"]
155 TRC,
156}
157impl CC3SR {
158 #[doc = r" Value of the field as raw bits"]
159 #[inline]
160 pub fn bits(&self) -> u8 {
161 match *self {
162 CC3SR::OUTPUT => 0,
163 CC3SR::TI3 => 1,
164 CC3SR::TI4 => 2,
165 CC3SR::TRC => 3,
166 }
167 }
168 #[allow(missing_docs)]
169 #[doc(hidden)]
170 #[inline]
171 pub fn _from(value: u8) -> CC3SR {
172 match value {
173 0 => CC3SR::OUTPUT,
174 1 => CC3SR::TI3,
175 2 => CC3SR::TI4,
176 3 => CC3SR::TRC,
177 _ => unreachable!(),
178 }
179 }
180 #[doc = "Checks if the value of the field is `OUTPUT`"]
181 #[inline]
182 pub fn is_output(&self) -> bool {
183 *self == CC3SR::OUTPUT
184 }
185 #[doc = "Checks if the value of the field is `TI3`"]
186 #[inline]
187 pub fn is_ti3(&self) -> bool {
188 *self == CC3SR::TI3
189 }
190 #[doc = "Checks if the value of the field is `TI4`"]
191 #[inline]
192 pub fn is_ti4(&self) -> bool {
193 *self == CC3SR::TI4
194 }
195 #[doc = "Checks if the value of the field is `TRC`"]
196 #[inline]
197 pub fn is_trc(&self) -> bool {
198 *self == CC3SR::TRC
199 }
200}
201#[doc = r" Proxy"]
202pub struct _IC4FW<'a> {
203 w: &'a mut W,
204}
205impl<'a> _IC4FW<'a> {
206 #[doc = r" Writes raw bits to the field"]
207 #[inline]
208 pub fn bits(self, value: u8) -> &'a mut W {
209 const MASK: u8 = 15;
210 const OFFSET: u8 = 12;
211 self.w.bits &= !((MASK as u32) << OFFSET);
212 self.w.bits |= ((value & MASK) as u32) << OFFSET;
213 self.w
214 }
215}
216#[doc = r" Proxy"]
217pub struct _IC4PSCW<'a> {
218 w: &'a mut W,
219}
220impl<'a> _IC4PSCW<'a> {
221 #[doc = r" Writes raw bits to the field"]
222 #[inline]
223 pub fn bits(self, value: u8) -> &'a mut W {
224 const MASK: u8 = 3;
225 const OFFSET: u8 = 10;
226 self.w.bits &= !((MASK as u32) << OFFSET);
227 self.w.bits |= ((value & MASK) as u32) << OFFSET;
228 self.w
229 }
230}
231#[doc = "Values that can be written to the field `CC4S`"]
232pub enum CC4SW {
233 #[doc = "CC4 channel is configured as output"]
234 OUTPUT,
235 #[doc = "CC4 channel is configured as input, IC4 is mapped on TI4"]
236 TI4,
237 #[doc = "CC4 channel is configured as input, IC4 is mapped on TI3"]
238 TI3,
239 #[doc = "CC4 channel is configured as input, IC4 is mapped on TRC"]
240 TRC,
241}
242impl CC4SW {
243 #[allow(missing_docs)]
244 #[doc(hidden)]
245 #[inline]
246 pub fn _bits(&self) -> u8 {
247 match *self {
248 CC4SW::OUTPUT => 0,
249 CC4SW::TI4 => 1,
250 CC4SW::TI3 => 2,
251 CC4SW::TRC => 3,
252 }
253 }
254}
255#[doc = r" Proxy"]
256pub struct _CC4SW<'a> {
257 w: &'a mut W,
258}
259impl<'a> _CC4SW<'a> {
260 #[doc = r" Writes `variant` to the field"]
261 #[inline]
262 pub fn variant(self, variant: CC4SW) -> &'a mut W {
263 {
264 self.bits(variant._bits())
265 }
266 }
267 #[doc = "CC4 channel is configured as output"]
268 #[inline]
269 pub fn output(self) -> &'a mut W {
270 self.variant(CC4SW::OUTPUT)
271 }
272 #[doc = "CC4 channel is configured as input, IC4 is mapped on TI4"]
273 #[inline]
274 pub fn ti4(self) -> &'a mut W {
275 self.variant(CC4SW::TI4)
276 }
277 #[doc = "CC4 channel is configured as input, IC4 is mapped on TI3"]
278 #[inline]
279 pub fn ti3(self) -> &'a mut W {
280 self.variant(CC4SW::TI3)
281 }
282 #[doc = "CC4 channel is configured as input, IC4 is mapped on TRC"]
283 #[inline]
284 pub fn trc(self) -> &'a mut W {
285 self.variant(CC4SW::TRC)
286 }
287 #[doc = r" Writes raw bits to the field"]
288 #[inline]
289 pub fn bits(self, value: u8) -> &'a mut W {
290 const MASK: u8 = 3;
291 const OFFSET: u8 = 8;
292 self.w.bits &= !((MASK as u32) << OFFSET);
293 self.w.bits |= ((value & MASK) as u32) << OFFSET;
294 self.w
295 }
296}
297#[doc = r" Proxy"]
298pub struct _IC3FW<'a> {
299 w: &'a mut W,
300}
301impl<'a> _IC3FW<'a> {
302 #[doc = r" Writes raw bits to the field"]
303 #[inline]
304 pub fn bits(self, value: u8) -> &'a mut W {
305 const MASK: u8 = 15;
306 const OFFSET: u8 = 4;
307 self.w.bits &= !((MASK as u32) << OFFSET);
308 self.w.bits |= ((value & MASK) as u32) << OFFSET;
309 self.w
310 }
311}
312#[doc = r" Proxy"]
313pub struct _IC3PSCW<'a> {
314 w: &'a mut W,
315}
316impl<'a> _IC3PSCW<'a> {
317 #[doc = r" Writes raw bits to the field"]
318 #[inline]
319 pub fn bits(self, value: u8) -> &'a mut W {
320 const MASK: u8 = 3;
321 const OFFSET: u8 = 2;
322 self.w.bits &= !((MASK as u32) << OFFSET);
323 self.w.bits |= ((value & MASK) as u32) << OFFSET;
324 self.w
325 }
326}
327#[doc = "Values that can be written to the field `CC3S`"]
328pub enum CC3SW {
329 #[doc = "CC3 channel is configured as output"]
330 OUTPUT,
331 #[doc = "CC3 channel is configured as input, IC3 is mapped on TI3"]
332 TI3,
333 #[doc = "CC3 channel is configured as input, IC3 is mapped on TI4"]
334 TI4,
335 #[doc = "CC3 channel is configured as input, IC3 is mapped on TRC"]
336 TRC,
337}
338impl CC3SW {
339 #[allow(missing_docs)]
340 #[doc(hidden)]
341 #[inline]
342 pub fn _bits(&self) -> u8 {
343 match *self {
344 CC3SW::OUTPUT => 0,
345 CC3SW::TI3 => 1,
346 CC3SW::TI4 => 2,
347 CC3SW::TRC => 3,
348 }
349 }
350}
351#[doc = r" Proxy"]
352pub struct _CC3SW<'a> {
353 w: &'a mut W,
354}
355impl<'a> _CC3SW<'a> {
356 #[doc = r" Writes `variant` to the field"]
357 #[inline]
358 pub fn variant(self, variant: CC3SW) -> &'a mut W {
359 {
360 self.bits(variant._bits())
361 }
362 }
363 #[doc = "CC3 channel is configured as output"]
364 #[inline]
365 pub fn output(self) -> &'a mut W {
366 self.variant(CC3SW::OUTPUT)
367 }
368 #[doc = "CC3 channel is configured as input, IC3 is mapped on TI3"]
369 #[inline]
370 pub fn ti3(self) -> &'a mut W {
371 self.variant(CC3SW::TI3)
372 }
373 #[doc = "CC3 channel is configured as input, IC3 is mapped on TI4"]
374 #[inline]
375 pub fn ti4(self) -> &'a mut W {
376 self.variant(CC3SW::TI4)
377 }
378 #[doc = "CC3 channel is configured as input, IC3 is mapped on TRC"]
379 #[inline]
380 pub fn trc(self) -> &'a mut W {
381 self.variant(CC3SW::TRC)
382 }
383 #[doc = r" Writes raw bits to the field"]
384 #[inline]
385 pub fn bits(self, value: u8) -> &'a mut W {
386 const MASK: u8 = 3;
387 const OFFSET: u8 = 0;
388 self.w.bits &= !((MASK as u32) << OFFSET);
389 self.w.bits |= ((value & MASK) as u32) << OFFSET;
390 self.w
391 }
392}
393impl R {
394 #[doc = r" Value of the register as raw bits"]
395 #[inline]
396 pub fn bits(&self) -> u32 {
397 self.bits
398 }
399 #[doc = "Bits 12:15 - Input capture 4 filter"]
400 #[inline]
401 pub fn ic4f(&self) -> IC4FR {
402 let bits = {
403 const MASK: u8 = 15;
404 const OFFSET: u8 = 12;
405 ((self.bits >> OFFSET) & MASK as u32) as u8
406 };
407 IC4FR { bits }
408 }
409 #[doc = "Bits 10:11 - Input capture 4 prescaler"]
410 #[inline]
411 pub fn ic4psc(&self) -> IC4PSCR {
412 let bits = {
413 const MASK: u8 = 3;
414 const OFFSET: u8 = 10;
415 ((self.bits >> OFFSET) & MASK as u32) as u8
416 };
417 IC4PSCR { bits }
418 }
419 #[doc = "Bits 8:9 - Capture/Compare 4 selection"]
420 #[inline]
421 pub fn cc4s(&self) -> CC4SR {
422 CC4SR::_from({
423 const MASK: u8 = 3;
424 const OFFSET: u8 = 8;
425 ((self.bits >> OFFSET) & MASK as u32) as u8
426 })
427 }
428 #[doc = "Bits 4:7 - Input capture 3 filter"]
429 #[inline]
430 pub fn ic3f(&self) -> IC3FR {
431 let bits = {
432 const MASK: u8 = 15;
433 const OFFSET: u8 = 4;
434 ((self.bits >> OFFSET) & MASK as u32) as u8
435 };
436 IC3FR { bits }
437 }
438 #[doc = "Bits 2:3 - Input capture 3 prescaler"]
439 #[inline]
440 pub fn ic3psc(&self) -> IC3PSCR {
441 let bits = {
442 const MASK: u8 = 3;
443 const OFFSET: u8 = 2;
444 ((self.bits >> OFFSET) & MASK as u32) as u8
445 };
446 IC3PSCR { bits }
447 }
448 #[doc = "Bits 0:1 - Capture/Compare 3 selection"]
449 #[inline]
450 pub fn cc3s(&self) -> CC3SR {
451 CC3SR::_from({
452 const MASK: u8 = 3;
453 const OFFSET: u8 = 0;
454 ((self.bits >> OFFSET) & MASK as u32) as u8
455 })
456 }
457}
458impl W {
459 #[doc = r" Reset value of the register"]
460 #[inline]
461 pub fn reset_value() -> W {
462 W { bits: 0 }
463 }
464 #[doc = r" Writes raw bits to the register"]
465 #[inline]
466 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
467 self.bits = bits;
468 self
469 }
470 #[doc = "Bits 12:15 - Input capture 4 filter"]
471 #[inline]
472 pub fn ic4f(&mut self) -> _IC4FW {
473 _IC4FW { w: self }
474 }
475 #[doc = "Bits 10:11 - Input capture 4 prescaler"]
476 #[inline]
477 pub fn ic4psc(&mut self) -> _IC4PSCW {
478 _IC4PSCW { w: self }
479 }
480 #[doc = "Bits 8:9 - Capture/Compare 4 selection"]
481 #[inline]
482 pub fn cc4s(&mut self) -> _CC4SW {
483 _CC4SW { w: self }
484 }
485 #[doc = "Bits 4:7 - Input capture 3 filter"]
486 #[inline]
487 pub fn ic3f(&mut self) -> _IC3FW {
488 _IC3FW { w: self }
489 }
490 #[doc = "Bits 2:3 - Input capture 3 prescaler"]
491 #[inline]
492 pub fn ic3psc(&mut self) -> _IC3PSCW {
493 _IC3PSCW { w: self }
494 }
495 #[doc = "Bits 0:1 - Capture/Compare 3 selection"]
496 #[inline]
497 pub fn cc3s(&mut self) -> _CC3SW {
498 _CC3SW { w: self }
499 }
500}