1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::CCMR1_INPUT {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = r" Value of the field"]
46pub struct IC2FR {
47 bits: u8,
48}
49impl IC2FR {
50 #[doc = r" Value of the field as raw bits"]
51 #[inline]
52 pub fn bits(&self) -> u8 {
53 self.bits
54 }
55}
56#[doc = r" Value of the field"]
57pub struct IC2PSCR {
58 bits: u8,
59}
60impl IC2PSCR {
61 #[doc = r" Value of the field as raw bits"]
62 #[inline]
63 pub fn bits(&self) -> u8 {
64 self.bits
65 }
66}
67#[doc = "Possible values of the field `CC2S`"]
68#[derive(Clone, Copy, Debug, PartialEq)]
69pub enum CC2SR {
70 #[doc = "CC2 channel is configured as output"]
71 OUTPUT,
72 #[doc = "CC2 channel is configured as input, IC2 is mapped on TI2"]
73 TI2,
74 #[doc = "CC2 channel is configured as input, IC2 is mapped on TI1"]
75 TI1,
76 #[doc = "CC2 channel is configured as input, IC2 is mapped on TRC"]
77 TRC,
78}
79impl CC2SR {
80 #[doc = r" Value of the field as raw bits"]
81 #[inline]
82 pub fn bits(&self) -> u8 {
83 match *self {
84 CC2SR::OUTPUT => 0,
85 CC2SR::TI2 => 1,
86 CC2SR::TI1 => 2,
87 CC2SR::TRC => 3,
88 }
89 }
90 #[allow(missing_docs)]
91 #[doc(hidden)]
92 #[inline]
93 pub fn _from(value: u8) -> CC2SR {
94 match value {
95 0 => CC2SR::OUTPUT,
96 1 => CC2SR::TI2,
97 2 => CC2SR::TI1,
98 3 => CC2SR::TRC,
99 _ => unreachable!(),
100 }
101 }
102 #[doc = "Checks if the value of the field is `OUTPUT`"]
103 #[inline]
104 pub fn is_output(&self) -> bool {
105 *self == CC2SR::OUTPUT
106 }
107 #[doc = "Checks if the value of the field is `TI2`"]
108 #[inline]
109 pub fn is_ti2(&self) -> bool {
110 *self == CC2SR::TI2
111 }
112 #[doc = "Checks if the value of the field is `TI1`"]
113 #[inline]
114 pub fn is_ti1(&self) -> bool {
115 *self == CC2SR::TI1
116 }
117 #[doc = "Checks if the value of the field is `TRC`"]
118 #[inline]
119 pub fn is_trc(&self) -> bool {
120 *self == CC2SR::TRC
121 }
122}
123#[doc = "Possible values of the field `IC1F`"]
124#[derive(Clone, Copy, Debug, PartialEq)]
125pub enum IC1FR {
126 #[doc = "No filter, sampling is done at fDTS"]
127 NOFILTER,
128 #[doc = "fSAMPLING=fCK_INT, N=2"]
129 FCK_INT_N2,
130 #[doc = "fSAMPLING=fCK_INT, N=4"]
131 FCK_INT_N4,
132 #[doc = "fSAMPLING=fCK_INT, N=8"]
133 FCK_INT_N8,
134 #[doc = "fSAMPLING=fDTS/2, N=6"]
135 FDTS_DIV2_N6,
136 #[doc = "fSAMPLING=fDTS/2, N=8"]
137 FDTS_DIV2_N8,
138 #[doc = "fSAMPLING=fDTS/4, N=6"]
139 FDTS_DIV4_N6,
140 #[doc = "fSAMPLING=fDTS/4, N=8"]
141 FDTS_DIV4_N8,
142 #[doc = "fSAMPLING=fDTS/8, N=6"]
143 FDTS_DIV8_N6,
144 #[doc = "fSAMPLING=fDTS/8, N=8"]
145 FDTS_DIV8_N8,
146 #[doc = "fSAMPLING=fDTS/16, N=5"]
147 FDTS_DIV16_N5,
148 #[doc = "fSAMPLING=fDTS/16, N=6"]
149 FDTS_DIV16_N6,
150 #[doc = "fSAMPLING=fDTS/16, N=8"]
151 FDTS_DIV16_N8,
152 #[doc = "fSAMPLING=fDTS/32, N=5"]
153 FDTS_DIV32_N5,
154 #[doc = "fSAMPLING=fDTS/32, N=6"]
155 FDTS_DIV32_N6,
156 #[doc = "fSAMPLING=fDTS/32, N=8"]
157 FDTS_DIV32_N8,
158}
159impl IC1FR {
160 #[doc = r" Value of the field as raw bits"]
161 #[inline]
162 pub fn bits(&self) -> u8 {
163 match *self {
164 IC1FR::NOFILTER => 0,
165 IC1FR::FCK_INT_N2 => 1,
166 IC1FR::FCK_INT_N4 => 2,
167 IC1FR::FCK_INT_N8 => 3,
168 IC1FR::FDTS_DIV2_N6 => 4,
169 IC1FR::FDTS_DIV2_N8 => 5,
170 IC1FR::FDTS_DIV4_N6 => 6,
171 IC1FR::FDTS_DIV4_N8 => 7,
172 IC1FR::FDTS_DIV8_N6 => 8,
173 IC1FR::FDTS_DIV8_N8 => 9,
174 IC1FR::FDTS_DIV16_N5 => 10,
175 IC1FR::FDTS_DIV16_N6 => 11,
176 IC1FR::FDTS_DIV16_N8 => 12,
177 IC1FR::FDTS_DIV32_N5 => 13,
178 IC1FR::FDTS_DIV32_N6 => 14,
179 IC1FR::FDTS_DIV32_N8 => 15,
180 }
181 }
182 #[allow(missing_docs)]
183 #[doc(hidden)]
184 #[inline]
185 pub fn _from(value: u8) -> IC1FR {
186 match value {
187 0 => IC1FR::NOFILTER,
188 1 => IC1FR::FCK_INT_N2,
189 2 => IC1FR::FCK_INT_N4,
190 3 => IC1FR::FCK_INT_N8,
191 4 => IC1FR::FDTS_DIV2_N6,
192 5 => IC1FR::FDTS_DIV2_N8,
193 6 => IC1FR::FDTS_DIV4_N6,
194 7 => IC1FR::FDTS_DIV4_N8,
195 8 => IC1FR::FDTS_DIV8_N6,
196 9 => IC1FR::FDTS_DIV8_N8,
197 10 => IC1FR::FDTS_DIV16_N5,
198 11 => IC1FR::FDTS_DIV16_N6,
199 12 => IC1FR::FDTS_DIV16_N8,
200 13 => IC1FR::FDTS_DIV32_N5,
201 14 => IC1FR::FDTS_DIV32_N6,
202 15 => IC1FR::FDTS_DIV32_N8,
203 _ => unreachable!(),
204 }
205 }
206 #[doc = "Checks if the value of the field is `NOFILTER`"]
207 #[inline]
208 pub fn is_no_filter(&self) -> bool {
209 *self == IC1FR::NOFILTER
210 }
211 #[doc = "Checks if the value of the field is `FCK_INT_N2`"]
212 #[inline]
213 pub fn is_fck_int_n2(&self) -> bool {
214 *self == IC1FR::FCK_INT_N2
215 }
216 #[doc = "Checks if the value of the field is `FCK_INT_N4`"]
217 #[inline]
218 pub fn is_fck_int_n4(&self) -> bool {
219 *self == IC1FR::FCK_INT_N4
220 }
221 #[doc = "Checks if the value of the field is `FCK_INT_N8`"]
222 #[inline]
223 pub fn is_fck_int_n8(&self) -> bool {
224 *self == IC1FR::FCK_INT_N8
225 }
226 #[doc = "Checks if the value of the field is `FDTS_DIV2_N6`"]
227 #[inline]
228 pub fn is_fdts_div2_n6(&self) -> bool {
229 *self == IC1FR::FDTS_DIV2_N6
230 }
231 #[doc = "Checks if the value of the field is `FDTS_DIV2_N8`"]
232 #[inline]
233 pub fn is_fdts_div2_n8(&self) -> bool {
234 *self == IC1FR::FDTS_DIV2_N8
235 }
236 #[doc = "Checks if the value of the field is `FDTS_DIV4_N6`"]
237 #[inline]
238 pub fn is_fdts_div4_n6(&self) -> bool {
239 *self == IC1FR::FDTS_DIV4_N6
240 }
241 #[doc = "Checks if the value of the field is `FDTS_DIV4_N8`"]
242 #[inline]
243 pub fn is_fdts_div4_n8(&self) -> bool {
244 *self == IC1FR::FDTS_DIV4_N8
245 }
246 #[doc = "Checks if the value of the field is `FDTS_DIV8_N6`"]
247 #[inline]
248 pub fn is_fdts_div8_n6(&self) -> bool {
249 *self == IC1FR::FDTS_DIV8_N6
250 }
251 #[doc = "Checks if the value of the field is `FDTS_DIV8_N8`"]
252 #[inline]
253 pub fn is_fdts_div8_n8(&self) -> bool {
254 *self == IC1FR::FDTS_DIV8_N8
255 }
256 #[doc = "Checks if the value of the field is `FDTS_DIV16_N5`"]
257 #[inline]
258 pub fn is_fdts_div16_n5(&self) -> bool {
259 *self == IC1FR::FDTS_DIV16_N5
260 }
261 #[doc = "Checks if the value of the field is `FDTS_DIV16_N6`"]
262 #[inline]
263 pub fn is_fdts_div16_n6(&self) -> bool {
264 *self == IC1FR::FDTS_DIV16_N6
265 }
266 #[doc = "Checks if the value of the field is `FDTS_DIV16_N8`"]
267 #[inline]
268 pub fn is_fdts_div16_n8(&self) -> bool {
269 *self == IC1FR::FDTS_DIV16_N8
270 }
271 #[doc = "Checks if the value of the field is `FDTS_DIV32_N5`"]
272 #[inline]
273 pub fn is_fdts_div32_n5(&self) -> bool {
274 *self == IC1FR::FDTS_DIV32_N5
275 }
276 #[doc = "Checks if the value of the field is `FDTS_DIV32_N6`"]
277 #[inline]
278 pub fn is_fdts_div32_n6(&self) -> bool {
279 *self == IC1FR::FDTS_DIV32_N6
280 }
281 #[doc = "Checks if the value of the field is `FDTS_DIV32_N8`"]
282 #[inline]
283 pub fn is_fdts_div32_n8(&self) -> bool {
284 *self == IC1FR::FDTS_DIV32_N8
285 }
286}
287#[doc = r" Value of the field"]
288pub struct IC1PSCR {
289 bits: u8,
290}
291impl IC1PSCR {
292 #[doc = r" Value of the field as raw bits"]
293 #[inline]
294 pub fn bits(&self) -> u8 {
295 self.bits
296 }
297}
298#[doc = "Possible values of the field `CC1S`"]
299#[derive(Clone, Copy, Debug, PartialEq)]
300pub enum CC1SR {
301 #[doc = "CC1 channel is configured as output"]
302 OUTPUT,
303 #[doc = "CC1 channel is configured as input, IC1 is mapped on TI1"]
304 TI1,
305 #[doc = "CC1 channel is configured as input, IC1 is mapped on TI2"]
306 TI2,
307 #[doc = "CC1 channel is configured as input, IC1 is mapped on TRC"]
308 TRC,
309}
310impl CC1SR {
311 #[doc = r" Value of the field as raw bits"]
312 #[inline]
313 pub fn bits(&self) -> u8 {
314 match *self {
315 CC1SR::OUTPUT => 0,
316 CC1SR::TI1 => 1,
317 CC1SR::TI2 => 2,
318 CC1SR::TRC => 3,
319 }
320 }
321 #[allow(missing_docs)]
322 #[doc(hidden)]
323 #[inline]
324 pub fn _from(value: u8) -> CC1SR {
325 match value {
326 0 => CC1SR::OUTPUT,
327 1 => CC1SR::TI1,
328 2 => CC1SR::TI2,
329 3 => CC1SR::TRC,
330 _ => unreachable!(),
331 }
332 }
333 #[doc = "Checks if the value of the field is `OUTPUT`"]
334 #[inline]
335 pub fn is_output(&self) -> bool {
336 *self == CC1SR::OUTPUT
337 }
338 #[doc = "Checks if the value of the field is `TI1`"]
339 #[inline]
340 pub fn is_ti1(&self) -> bool {
341 *self == CC1SR::TI1
342 }
343 #[doc = "Checks if the value of the field is `TI2`"]
344 #[inline]
345 pub fn is_ti2(&self) -> bool {
346 *self == CC1SR::TI2
347 }
348 #[doc = "Checks if the value of the field is `TRC`"]
349 #[inline]
350 pub fn is_trc(&self) -> bool {
351 *self == CC1SR::TRC
352 }
353}
354#[doc = r" Proxy"]
355pub struct _IC2FW<'a> {
356 w: &'a mut W,
357}
358impl<'a> _IC2FW<'a> {
359 #[doc = r" Writes raw bits to the field"]
360 #[inline]
361 pub fn bits(self, value: u8) -> &'a mut W {
362 const MASK: u8 = 15;
363 const OFFSET: u8 = 12;
364 self.w.bits &= !((MASK as u32) << OFFSET);
365 self.w.bits |= ((value & MASK) as u32) << OFFSET;
366 self.w
367 }
368}
369#[doc = r" Proxy"]
370pub struct _IC2PSCW<'a> {
371 w: &'a mut W,
372}
373impl<'a> _IC2PSCW<'a> {
374 #[doc = r" Writes raw bits to the field"]
375 #[inline]
376 pub unsafe fn bits(self, value: u8) -> &'a mut W {
377 const MASK: u8 = 3;
378 const OFFSET: u8 = 10;
379 self.w.bits &= !((MASK as u32) << OFFSET);
380 self.w.bits |= ((value & MASK) as u32) << OFFSET;
381 self.w
382 }
383}
384#[doc = "Values that can be written to the field `CC2S`"]
385pub enum CC2SW {
386 #[doc = "CC2 channel is configured as output"]
387 OUTPUT,
388 #[doc = "CC2 channel is configured as input, IC2 is mapped on TI2"]
389 TI2,
390 #[doc = "CC2 channel is configured as input, IC2 is mapped on TI1"]
391 TI1,
392 #[doc = "CC2 channel is configured as input, IC2 is mapped on TRC"]
393 TRC,
394}
395impl CC2SW {
396 #[allow(missing_docs)]
397 #[doc(hidden)]
398 #[inline]
399 pub fn _bits(&self) -> u8 {
400 match *self {
401 CC2SW::OUTPUT => 0,
402 CC2SW::TI2 => 1,
403 CC2SW::TI1 => 2,
404 CC2SW::TRC => 3,
405 }
406 }
407}
408#[doc = r" Proxy"]
409pub struct _CC2SW<'a> {
410 w: &'a mut W,
411}
412impl<'a> _CC2SW<'a> {
413 #[doc = r" Writes `variant` to the field"]
414 #[inline]
415 pub fn variant(self, variant: CC2SW) -> &'a mut W {
416 {
417 self.bits(variant._bits())
418 }
419 }
420 #[doc = "CC2 channel is configured as output"]
421 #[inline]
422 pub fn output(self) -> &'a mut W {
423 self.variant(CC2SW::OUTPUT)
424 }
425 #[doc = "CC2 channel is configured as input, IC2 is mapped on TI2"]
426 #[inline]
427 pub fn ti2(self) -> &'a mut W {
428 self.variant(CC2SW::TI2)
429 }
430 #[doc = "CC2 channel is configured as input, IC2 is mapped on TI1"]
431 #[inline]
432 pub fn ti1(self) -> &'a mut W {
433 self.variant(CC2SW::TI1)
434 }
435 #[doc = "CC2 channel is configured as input, IC2 is mapped on TRC"]
436 #[inline]
437 pub fn trc(self) -> &'a mut W {
438 self.variant(CC2SW::TRC)
439 }
440 #[doc = r" Writes raw bits to the field"]
441 #[inline]
442 pub fn bits(self, value: u8) -> &'a mut W {
443 const MASK: u8 = 3;
444 const OFFSET: u8 = 8;
445 self.w.bits &= !((MASK as u32) << OFFSET);
446 self.w.bits |= ((value & MASK) as u32) << OFFSET;
447 self.w
448 }
449}
450#[doc = "Values that can be written to the field `IC1F`"]
451pub enum IC1FW {
452 #[doc = "No filter, sampling is done at fDTS"]
453 NOFILTER,
454 #[doc = "fSAMPLING=fCK_INT, N=2"]
455 FCK_INT_N2,
456 #[doc = "fSAMPLING=fCK_INT, N=4"]
457 FCK_INT_N4,
458 #[doc = "fSAMPLING=fCK_INT, N=8"]
459 FCK_INT_N8,
460 #[doc = "fSAMPLING=fDTS/2, N=6"]
461 FDTS_DIV2_N6,
462 #[doc = "fSAMPLING=fDTS/2, N=8"]
463 FDTS_DIV2_N8,
464 #[doc = "fSAMPLING=fDTS/4, N=6"]
465 FDTS_DIV4_N6,
466 #[doc = "fSAMPLING=fDTS/4, N=8"]
467 FDTS_DIV4_N8,
468 #[doc = "fSAMPLING=fDTS/8, N=6"]
469 FDTS_DIV8_N6,
470 #[doc = "fSAMPLING=fDTS/8, N=8"]
471 FDTS_DIV8_N8,
472 #[doc = "fSAMPLING=fDTS/16, N=5"]
473 FDTS_DIV16_N5,
474 #[doc = "fSAMPLING=fDTS/16, N=6"]
475 FDTS_DIV16_N6,
476 #[doc = "fSAMPLING=fDTS/16, N=8"]
477 FDTS_DIV16_N8,
478 #[doc = "fSAMPLING=fDTS/32, N=5"]
479 FDTS_DIV32_N5,
480 #[doc = "fSAMPLING=fDTS/32, N=6"]
481 FDTS_DIV32_N6,
482 #[doc = "fSAMPLING=fDTS/32, N=8"]
483 FDTS_DIV32_N8,
484}
485impl IC1FW {
486 #[allow(missing_docs)]
487 #[doc(hidden)]
488 #[inline]
489 pub fn _bits(&self) -> u8 {
490 match *self {
491 IC1FW::NOFILTER => 0,
492 IC1FW::FCK_INT_N2 => 1,
493 IC1FW::FCK_INT_N4 => 2,
494 IC1FW::FCK_INT_N8 => 3,
495 IC1FW::FDTS_DIV2_N6 => 4,
496 IC1FW::FDTS_DIV2_N8 => 5,
497 IC1FW::FDTS_DIV4_N6 => 6,
498 IC1FW::FDTS_DIV4_N8 => 7,
499 IC1FW::FDTS_DIV8_N6 => 8,
500 IC1FW::FDTS_DIV8_N8 => 9,
501 IC1FW::FDTS_DIV16_N5 => 10,
502 IC1FW::FDTS_DIV16_N6 => 11,
503 IC1FW::FDTS_DIV16_N8 => 12,
504 IC1FW::FDTS_DIV32_N5 => 13,
505 IC1FW::FDTS_DIV32_N6 => 14,
506 IC1FW::FDTS_DIV32_N8 => 15,
507 }
508 }
509}
510#[doc = r" Proxy"]
511pub struct _IC1FW<'a> {
512 w: &'a mut W,
513}
514impl<'a> _IC1FW<'a> {
515 #[doc = r" Writes `variant` to the field"]
516 #[inline]
517 pub fn variant(self, variant: IC1FW) -> &'a mut W {
518 {
519 self.bits(variant._bits())
520 }
521 }
522 #[doc = "No filter, sampling is done at fDTS"]
523 #[inline]
524 pub fn no_filter(self) -> &'a mut W {
525 self.variant(IC1FW::NOFILTER)
526 }
527 #[doc = "fSAMPLING=fCK_INT, N=2"]
528 #[inline]
529 pub fn fck_int_n2(self) -> &'a mut W {
530 self.variant(IC1FW::FCK_INT_N2)
531 }
532 #[doc = "fSAMPLING=fCK_INT, N=4"]
533 #[inline]
534 pub fn fck_int_n4(self) -> &'a mut W {
535 self.variant(IC1FW::FCK_INT_N4)
536 }
537 #[doc = "fSAMPLING=fCK_INT, N=8"]
538 #[inline]
539 pub fn fck_int_n8(self) -> &'a mut W {
540 self.variant(IC1FW::FCK_INT_N8)
541 }
542 #[doc = "fSAMPLING=fDTS/2, N=6"]
543 #[inline]
544 pub fn fdts_div2_n6(self) -> &'a mut W {
545 self.variant(IC1FW::FDTS_DIV2_N6)
546 }
547 #[doc = "fSAMPLING=fDTS/2, N=8"]
548 #[inline]
549 pub fn fdts_div2_n8(self) -> &'a mut W {
550 self.variant(IC1FW::FDTS_DIV2_N8)
551 }
552 #[doc = "fSAMPLING=fDTS/4, N=6"]
553 #[inline]
554 pub fn fdts_div4_n6(self) -> &'a mut W {
555 self.variant(IC1FW::FDTS_DIV4_N6)
556 }
557 #[doc = "fSAMPLING=fDTS/4, N=8"]
558 #[inline]
559 pub fn fdts_div4_n8(self) -> &'a mut W {
560 self.variant(IC1FW::FDTS_DIV4_N8)
561 }
562 #[doc = "fSAMPLING=fDTS/8, N=6"]
563 #[inline]
564 pub fn fdts_div8_n6(self) -> &'a mut W {
565 self.variant(IC1FW::FDTS_DIV8_N6)
566 }
567 #[doc = "fSAMPLING=fDTS/8, N=8"]
568 #[inline]
569 pub fn fdts_div8_n8(self) -> &'a mut W {
570 self.variant(IC1FW::FDTS_DIV8_N8)
571 }
572 #[doc = "fSAMPLING=fDTS/16, N=5"]
573 #[inline]
574 pub fn fdts_div16_n5(self) -> &'a mut W {
575 self.variant(IC1FW::FDTS_DIV16_N5)
576 }
577 #[doc = "fSAMPLING=fDTS/16, N=6"]
578 #[inline]
579 pub fn fdts_div16_n6(self) -> &'a mut W {
580 self.variant(IC1FW::FDTS_DIV16_N6)
581 }
582 #[doc = "fSAMPLING=fDTS/16, N=8"]
583 #[inline]
584 pub fn fdts_div16_n8(self) -> &'a mut W {
585 self.variant(IC1FW::FDTS_DIV16_N8)
586 }
587 #[doc = "fSAMPLING=fDTS/32, N=5"]
588 #[inline]
589 pub fn fdts_div32_n5(self) -> &'a mut W {
590 self.variant(IC1FW::FDTS_DIV32_N5)
591 }
592 #[doc = "fSAMPLING=fDTS/32, N=6"]
593 #[inline]
594 pub fn fdts_div32_n6(self) -> &'a mut W {
595 self.variant(IC1FW::FDTS_DIV32_N6)
596 }
597 #[doc = "fSAMPLING=fDTS/32, N=8"]
598 #[inline]
599 pub fn fdts_div32_n8(self) -> &'a mut W {
600 self.variant(IC1FW::FDTS_DIV32_N8)
601 }
602 #[doc = r" Writes raw bits to the field"]
603 #[inline]
604 pub fn bits(self, value: u8) -> &'a mut W {
605 const MASK: u8 = 15;
606 const OFFSET: u8 = 4;
607 self.w.bits &= !((MASK as u32) << OFFSET);
608 self.w.bits |= ((value & MASK) as u32) << OFFSET;
609 self.w
610 }
611}
612#[doc = r" Proxy"]
613pub struct _IC1PSCW<'a> {
614 w: &'a mut W,
615}
616impl<'a> _IC1PSCW<'a> {
617 #[doc = r" Writes raw bits to the field"]
618 #[inline]
619 pub unsafe fn bits(self, value: u8) -> &'a mut W {
620 const MASK: u8 = 3;
621 const OFFSET: u8 = 2;
622 self.w.bits &= !((MASK as u32) << OFFSET);
623 self.w.bits |= ((value & MASK) as u32) << OFFSET;
624 self.w
625 }
626}
627#[doc = "Values that can be written to the field `CC1S`"]
628pub enum CC1SW {
629 #[doc = "CC1 channel is configured as output"]
630 OUTPUT,
631 #[doc = "CC1 channel is configured as input, IC1 is mapped on TI1"]
632 TI1,
633 #[doc = "CC1 channel is configured as input, IC1 is mapped on TI2"]
634 TI2,
635 #[doc = "CC1 channel is configured as input, IC1 is mapped on TRC"]
636 TRC,
637}
638impl CC1SW {
639 #[allow(missing_docs)]
640 #[doc(hidden)]
641 #[inline]
642 pub fn _bits(&self) -> u8 {
643 match *self {
644 CC1SW::OUTPUT => 0,
645 CC1SW::TI1 => 1,
646 CC1SW::TI2 => 2,
647 CC1SW::TRC => 3,
648 }
649 }
650}
651#[doc = r" Proxy"]
652pub struct _CC1SW<'a> {
653 w: &'a mut W,
654}
655impl<'a> _CC1SW<'a> {
656 #[doc = r" Writes `variant` to the field"]
657 #[inline]
658 pub fn variant(self, variant: CC1SW) -> &'a mut W {
659 {
660 self.bits(variant._bits())
661 }
662 }
663 #[doc = "CC1 channel is configured as output"]
664 #[inline]
665 pub fn output(self) -> &'a mut W {
666 self.variant(CC1SW::OUTPUT)
667 }
668 #[doc = "CC1 channel is configured as input, IC1 is mapped on TI1"]
669 #[inline]
670 pub fn ti1(self) -> &'a mut W {
671 self.variant(CC1SW::TI1)
672 }
673 #[doc = "CC1 channel is configured as input, IC1 is mapped on TI2"]
674 #[inline]
675 pub fn ti2(self) -> &'a mut W {
676 self.variant(CC1SW::TI2)
677 }
678 #[doc = "CC1 channel is configured as input, IC1 is mapped on TRC"]
679 #[inline]
680 pub fn trc(self) -> &'a mut W {
681 self.variant(CC1SW::TRC)
682 }
683 #[doc = r" Writes raw bits to the field"]
684 #[inline]
685 pub fn bits(self, value: u8) -> &'a mut W {
686 const MASK: u8 = 3;
687 const OFFSET: u8 = 0;
688 self.w.bits &= !((MASK as u32) << OFFSET);
689 self.w.bits |= ((value & MASK) as u32) << OFFSET;
690 self.w
691 }
692}
693impl R {
694 #[doc = r" Value of the register as raw bits"]
695 #[inline]
696 pub fn bits(&self) -> u32 {
697 self.bits
698 }
699 #[doc = "Bits 12:15 - Input capture 2 filter"]
700 #[inline]
701 pub fn ic2f(&self) -> IC2FR {
702 let bits = {
703 const MASK: u8 = 15;
704 const OFFSET: u8 = 12;
705 ((self.bits >> OFFSET) & MASK as u32) as u8
706 };
707 IC2FR { bits }
708 }
709 #[doc = "Bits 10:11 - Input capture 2 prescaler"]
710 #[inline]
711 pub fn ic2psc(&self) -> IC2PSCR {
712 let bits = {
713 const MASK: u8 = 3;
714 const OFFSET: u8 = 10;
715 ((self.bits >> OFFSET) & MASK as u32) as u8
716 };
717 IC2PSCR { bits }
718 }
719 #[doc = "Bits 8:9 - Capture/compare 2 selection"]
720 #[inline]
721 pub fn cc2s(&self) -> CC2SR {
722 CC2SR::_from({
723 const MASK: u8 = 3;
724 const OFFSET: u8 = 8;
725 ((self.bits >> OFFSET) & MASK as u32) as u8
726 })
727 }
728 #[doc = "Bits 4:7 - Input capture 1 filter"]
729 #[inline]
730 pub fn ic1f(&self) -> IC1FR {
731 IC1FR::_from({
732 const MASK: u8 = 15;
733 const OFFSET: u8 = 4;
734 ((self.bits >> OFFSET) & MASK as u32) as u8
735 })
736 }
737 #[doc = "Bits 2:3 - Input capture 1 prescaler"]
738 #[inline]
739 pub fn ic1psc(&self) -> IC1PSCR {
740 let bits = {
741 const MASK: u8 = 3;
742 const OFFSET: u8 = 2;
743 ((self.bits >> OFFSET) & MASK as u32) as u8
744 };
745 IC1PSCR { bits }
746 }
747 #[doc = "Bits 0:1 - Capture/Compare 1 selection"]
748 #[inline]
749 pub fn cc1s(&self) -> CC1SR {
750 CC1SR::_from({
751 const MASK: u8 = 3;
752 const OFFSET: u8 = 0;
753 ((self.bits >> OFFSET) & MASK as u32) as u8
754 })
755 }
756}
757impl W {
758 #[doc = r" Reset value of the register"]
759 #[inline]
760 pub fn reset_value() -> W {
761 W { bits: 0 }
762 }
763 #[doc = r" Writes raw bits to the register"]
764 #[inline]
765 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
766 self.bits = bits;
767 self
768 }
769 #[doc = "Bits 12:15 - Input capture 2 filter"]
770 #[inline]
771 pub fn ic2f(&mut self) -> _IC2FW {
772 _IC2FW { w: self }
773 }
774 #[doc = "Bits 10:11 - Input capture 2 prescaler"]
775 #[inline]
776 pub fn ic2psc(&mut self) -> _IC2PSCW {
777 _IC2PSCW { w: self }
778 }
779 #[doc = "Bits 8:9 - Capture/compare 2 selection"]
780 #[inline]
781 pub fn cc2s(&mut self) -> _CC2SW {
782 _CC2SW { w: self }
783 }
784 #[doc = "Bits 4:7 - Input capture 1 filter"]
785 #[inline]
786 pub fn ic1f(&mut self) -> _IC1FW {
787 _IC1FW { w: self }
788 }
789 #[doc = "Bits 2:3 - Input capture 1 prescaler"]
790 #[inline]
791 pub fn ic1psc(&mut self) -> _IC1PSCW {
792 _IC1PSCW { w: self }
793 }
794 #[doc = "Bits 0:1 - Capture/Compare 1 selection"]
795 #[inline]
796 pub fn cc1s(&mut self) -> _CC1SW {
797 _CC1SW { w: self }
798 }
799}