1#[doc = r" Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "0x00 - control register 1"]
5 pub cr1: CR1,
6 #[doc = "0x04 - control register 2"]
7 pub cr2: CR2,
8 #[doc = "0x08 - slave mode control register"]
9 pub smcr: SMCR,
10 #[doc = "0x0c - DMA/Interrupt enable register"]
11 pub dier: DIER,
12 #[doc = "0x10 - status register"]
13 pub sr: SR,
14 #[doc = "0x14 - event generation register"]
15 pub egr: EGR,
16 #[doc = "0x18 - capture/compare mode register 1 (output mode)"]
17 pub ccmr1_output: CCMR1_OUTPUT,
18 #[doc = "0x1c - capture/compare mode register 2 (output mode)"]
19 pub ccmr2_output: CCMR2_OUTPUT,
20 #[doc = "0x20 - capture/compare enable register"]
21 pub ccer: CCER,
22 #[doc = "0x24 - counter"]
23 pub cnt: CNT,
24 #[doc = "0x28 - prescaler"]
25 pub psc: PSC,
26 #[doc = "0x2c - auto-reload register"]
27 pub arr: ARR,
28 _reserved0: [u8; 4usize],
29 #[doc = "0x34 - capture/compare register 1"]
30 pub ccr1: CCR,
31 #[doc = "0x38 - capture/compare register 1"]
32 pub ccr2: CCR,
33 #[doc = "0x3c - capture/compare register 1"]
34 pub ccr3: CCR,
35 #[doc = "0x40 - capture/compare register 1"]
36 pub ccr4: CCR,
37 _reserved1: [u8; 4usize],
38 #[doc = "0x48 - DMA control register"]
39 pub dcr: DCR,
40 #[doc = "0x4c - DMA address for full transfer"]
41 pub dmar: DMAR,
42 #[doc = "0x50 - TIM2 option register"]
43 pub or: OR,
44}
45#[doc = "control register 1"]
46pub struct CR1 {
47 register: ::vcell::VolatileCell<u32>,
48}
49#[doc = "control register 1"]
50pub mod cr1;
51#[doc = "control register 2"]
52pub struct CR2 {
53 register: ::vcell::VolatileCell<u32>,
54}
55#[doc = "control register 2"]
56pub mod cr2;
57#[doc = "slave mode control register"]
58pub struct SMCR {
59 register: ::vcell::VolatileCell<u32>,
60}
61#[doc = "slave mode control register"]
62pub mod smcr;
63#[doc = "DMA/Interrupt enable register"]
64pub struct DIER {
65 register: ::vcell::VolatileCell<u32>,
66}
67#[doc = "DMA/Interrupt enable register"]
68pub mod dier;
69#[doc = "status register"]
70pub struct SR {
71 register: ::vcell::VolatileCell<u32>,
72}
73#[doc = "status register"]
74pub mod sr;
75#[doc = "event generation register"]
76pub struct EGR {
77 register: ::vcell::VolatileCell<u32>,
78}
79#[doc = "event generation register"]
80pub mod egr;
81#[doc = "capture/compare mode register 1 (output mode)"]
82pub struct CCMR1_OUTPUT {
83 register: ::vcell::VolatileCell<u32>,
84}
85#[doc = "capture/compare mode register 1 (output mode)"]
86pub mod ccmr1_output;
87#[doc = "capture/compare mode register 1 (input mode)"]
88pub struct CCMR1_INPUT {
89 register: ::vcell::VolatileCell<u32>,
90}
91#[doc = "capture/compare mode register 1 (input mode)"]
92pub mod ccmr1_input;
93#[doc = "capture/compare mode register 2 (output mode)"]
94pub struct CCMR2_OUTPUT {
95 register: ::vcell::VolatileCell<u32>,
96}
97#[doc = "capture/compare mode register 2 (output mode)"]
98pub mod ccmr2_output;
99#[doc = "capture/compare mode register 2 (input mode)"]
100pub struct CCMR2_INPUT {
101 register: ::vcell::VolatileCell<u32>,
102}
103#[doc = "capture/compare mode register 2 (input mode)"]
104pub mod ccmr2_input;
105#[doc = "capture/compare enable register"]
106pub struct CCER {
107 register: ::vcell::VolatileCell<u32>,
108}
109#[doc = "capture/compare enable register"]
110pub mod ccer;
111#[doc = "counter"]
112pub struct CNT {
113 register: ::vcell::VolatileCell<u32>,
114}
115#[doc = "counter"]
116pub mod cnt;
117#[doc = "prescaler"]
118pub struct PSC {
119 register: ::vcell::VolatileCell<u32>,
120}
121#[doc = "prescaler"]
122pub mod psc;
123#[doc = "auto-reload register"]
124pub struct ARR {
125 register: ::vcell::VolatileCell<u32>,
126}
127#[doc = "auto-reload register"]
128pub mod arr;
129#[doc = "capture/compare register 1"]
130pub struct CCR {
131 register: ::vcell::VolatileCell<u32>,
132}
133#[doc = "capture/compare register 1"]
134pub mod ccr;
135#[doc = "DMA control register"]
136pub struct DCR {
137 register: ::vcell::VolatileCell<u32>,
138}
139#[doc = "DMA control register"]
140pub mod dcr;
141#[doc = "DMA address for full transfer"]
142pub struct DMAR {
143 register: ::vcell::VolatileCell<u32>,
144}
145#[doc = "DMA address for full transfer"]
146pub mod dmar;
147#[doc = "TIM2 option register"]
148pub struct OR {
149 register: ::vcell::VolatileCell<u32>,
150}
151#[doc = "TIM2 option register"]
152pub mod or;