stm32l4x2_pac/
tim15.rs

1#[doc = r" Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4    #[doc = "0x00 - control register 1"]
5    pub cr1: CR1,
6    #[doc = "0x04 - control register 2"]
7    pub cr2: CR2,
8    _reserved0: [u8; 4usize],
9    #[doc = "0x0c - DMA/Interrupt enable register"]
10    pub dier: DIER,
11    #[doc = "0x10 - status register"]
12    pub sr: SR,
13    #[doc = "0x14 - event generation register"]
14    pub egr: EGR,
15    #[doc = "0x18 - capture/compare mode register (output mode)"]
16    pub ccmr1_output: CCMR1_OUTPUT,
17    _reserved1: [u8; 4usize],
18    #[doc = "0x20 - capture/compare enable register"]
19    pub ccer: CCER,
20    #[doc = "0x24 - counter"]
21    pub cnt: CNT,
22    #[doc = "0x28 - prescaler"]
23    pub psc: PSC,
24    #[doc = "0x2c - auto-reload register"]
25    pub arr: ARR,
26    #[doc = "0x30 - repetition counter register"]
27    pub rcr: RCR,
28    #[doc = "0x34 - capture/compare register 1"]
29    pub ccr1: CCR1,
30    _reserved2: [u8; 12usize],
31    #[doc = "0x44 - break and dead-time register"]
32    pub bdtr: BDTR,
33    #[doc = "0x48 - DMA control register"]
34    pub dcr: DCR,
35    #[doc = "0x4c - DMA address for full transfer"]
36    pub dmar: DMAR,
37}
38#[doc = "control register 1"]
39pub struct CR1 {
40    register: ::vcell::VolatileCell<u32>,
41}
42#[doc = "control register 1"]
43pub mod cr1;
44#[doc = "control register 2"]
45pub struct CR2 {
46    register: ::vcell::VolatileCell<u32>,
47}
48#[doc = "control register 2"]
49pub mod cr2;
50#[doc = "DMA/Interrupt enable register"]
51pub struct DIER {
52    register: ::vcell::VolatileCell<u32>,
53}
54#[doc = "DMA/Interrupt enable register"]
55pub mod dier;
56#[doc = "status register"]
57pub struct SR {
58    register: ::vcell::VolatileCell<u32>,
59}
60#[doc = "status register"]
61pub mod sr;
62#[doc = "event generation register"]
63pub struct EGR {
64    register: ::vcell::VolatileCell<u32>,
65}
66#[doc = "event generation register"]
67pub mod egr;
68#[doc = "capture/compare mode register (output mode)"]
69pub struct CCMR1_OUTPUT {
70    register: ::vcell::VolatileCell<u32>,
71}
72#[doc = "capture/compare mode register (output mode)"]
73pub mod ccmr1_output;
74#[doc = "capture/compare mode register 1 (input mode)"]
75pub struct CCMR1_INPUT {
76    register: ::vcell::VolatileCell<u32>,
77}
78#[doc = "capture/compare mode register 1 (input mode)"]
79pub mod ccmr1_input;
80#[doc = "capture/compare enable register"]
81pub struct CCER {
82    register: ::vcell::VolatileCell<u32>,
83}
84#[doc = "capture/compare enable register"]
85pub mod ccer;
86#[doc = "counter"]
87pub struct CNT {
88    register: ::vcell::VolatileCell<u32>,
89}
90#[doc = "counter"]
91pub mod cnt;
92#[doc = "prescaler"]
93pub struct PSC {
94    register: ::vcell::VolatileCell<u32>,
95}
96#[doc = "prescaler"]
97pub mod psc;
98#[doc = "auto-reload register"]
99pub struct ARR {
100    register: ::vcell::VolatileCell<u32>,
101}
102#[doc = "auto-reload register"]
103pub mod arr;
104#[doc = "repetition counter register"]
105pub struct RCR {
106    register: ::vcell::VolatileCell<u32>,
107}
108#[doc = "repetition counter register"]
109pub mod rcr;
110#[doc = "capture/compare register 1"]
111pub struct CCR1 {
112    register: ::vcell::VolatileCell<u32>,
113}
114#[doc = "capture/compare register 1"]
115pub mod ccr1;
116#[doc = "break and dead-time register"]
117pub struct BDTR {
118    register: ::vcell::VolatileCell<u32>,
119}
120#[doc = "break and dead-time register"]
121pub mod bdtr;
122#[doc = "DMA control register"]
123pub struct DCR {
124    register: ::vcell::VolatileCell<u32>,
125}
126#[doc = "DMA control register"]
127pub mod dcr;
128#[doc = "DMA address for full transfer"]
129pub struct DMAR {
130    register: ::vcell::VolatileCell<u32>,
131}
132#[doc = "DMA address for full transfer"]
133pub mod dmar;
stm32l4x2_pac/tim15.rs

stm32l4x2_pac/
tim15.rs
