stm32l4x2_pac/tim1/
or1.rs

1#[doc = r" Value read from the register"]
2pub struct R {
3    bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7    bits: u32,
8}
9impl super::OR1 {
10    #[doc = r" Modifies the contents of the register"]
11    #[inline]
12    pub fn modify<F>(&self, f: F)
13    where
14        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15    {
16        let bits = self.register.get();
17        let r = R { bits: bits };
18        let mut w = W { bits: bits };
19        f(&r, &mut w);
20        self.register.set(w.bits);
21    }
22    #[doc = r" Reads the contents of the register"]
23    #[inline]
24    pub fn read(&self) -> R {
25        R {
26            bits: self.register.get(),
27        }
28    }
29    #[doc = r" Writes to the register"]
30    #[inline]
31    pub fn write<F>(&self, f: F)
32    where
33        F: FnOnce(&mut W) -> &mut W,
34    {
35        let mut w = W::reset_value();
36        f(&mut w);
37        self.register.set(w.bits);
38    }
39    #[doc = r" Writes the reset value to the register"]
40    #[inline]
41    pub fn reset(&self) {
42        self.write(|w| w)
43    }
44}
45#[doc = r" Value of the field"]
46pub struct ETR_ADC1_RMPR {
47    bits: u8,
48}
49impl ETR_ADC1_RMPR {
50    #[doc = r" Value of the field as raw bits"]
51    #[inline]
52    pub fn bits(&self) -> u8 {
53        self.bits
54    }
55}
56#[doc = r" Value of the field"]
57pub struct ETR_ADC3_RMPR {
58    bits: u8,
59}
60impl ETR_ADC3_RMPR {
61    #[doc = r" Value of the field as raw bits"]
62    #[inline]
63    pub fn bits(&self) -> u8 {
64        self.bits
65    }
66}
67#[doc = r" Value of the field"]
68pub struct TI1_RMPR {
69    bits: bool,
70}
71impl TI1_RMPR {
72    #[doc = r" Value of the field as raw bits"]
73    #[inline]
74    pub fn bit(&self) -> bool {
75        self.bits
76    }
77    #[doc = r" Returns `true` if the bit is clear (0)"]
78    #[inline]
79    pub fn bit_is_clear(&self) -> bool {
80        !self.bit()
81    }
82    #[doc = r" Returns `true` if the bit is set (1)"]
83    #[inline]
84    pub fn bit_is_set(&self) -> bool {
85        self.bit()
86    }
87}
88#[doc = r" Proxy"]
89pub struct _ETR_ADC1_RMPW<'a> {
90    w: &'a mut W,
91}
92impl<'a> _ETR_ADC1_RMPW<'a> {
93    #[doc = r" Writes raw bits to the field"]
94    #[inline]
95    pub unsafe fn bits(self, value: u8) -> &'a mut W {
96        const MASK: u8 = 3;
97        const OFFSET: u8 = 0;
98        self.w.bits &= !((MASK as u32) << OFFSET);
99        self.w.bits |= ((value & MASK) as u32) << OFFSET;
100        self.w
101    }
102}
103#[doc = r" Proxy"]
104pub struct _ETR_ADC3_RMPW<'a> {
105    w: &'a mut W,
106}
107impl<'a> _ETR_ADC3_RMPW<'a> {
108    #[doc = r" Writes raw bits to the field"]
109    #[inline]
110    pub unsafe fn bits(self, value: u8) -> &'a mut W {
111        const MASK: u8 = 3;
112        const OFFSET: u8 = 2;
113        self.w.bits &= !((MASK as u32) << OFFSET);
114        self.w.bits |= ((value & MASK) as u32) << OFFSET;
115        self.w
116    }
117}
118#[doc = r" Proxy"]
119pub struct _TI1_RMPW<'a> {
120    w: &'a mut W,
121}
122impl<'a> _TI1_RMPW<'a> {
123    #[doc = r" Sets the field bit"]
124    pub fn set_bit(self) -> &'a mut W {
125        self.bit(true)
126    }
127    #[doc = r" Clears the field bit"]
128    pub fn clear_bit(self) -> &'a mut W {
129        self.bit(false)
130    }
131    #[doc = r" Writes raw bits to the field"]
132    #[inline]
133    pub fn bit(self, value: bool) -> &'a mut W {
134        const MASK: bool = true;
135        const OFFSET: u8 = 4;
136        self.w.bits &= !((MASK as u32) << OFFSET);
137        self.w.bits |= ((value & MASK) as u32) << OFFSET;
138        self.w
139    }
140}
141impl R {
142    #[doc = r" Value of the register as raw bits"]
143    #[inline]
144    pub fn bits(&self) -> u32 {
145        self.bits
146    }
147    #[doc = "Bits 0:1 - External trigger remap on ADC1 analog watchdog"]
148    #[inline]
149    pub fn etr_adc1_rmp(&self) -> ETR_ADC1_RMPR {
150        let bits = {
151            const MASK: u8 = 3;
152            const OFFSET: u8 = 0;
153            ((self.bits >> OFFSET) & MASK as u32) as u8
154        };
155        ETR_ADC1_RMPR { bits }
156    }
157    #[doc = "Bits 2:3 - External trigger remap on ADC3 analog watchdog"]
158    #[inline]
159    pub fn etr_adc3_rmp(&self) -> ETR_ADC3_RMPR {
160        let bits = {
161            const MASK: u8 = 3;
162            const OFFSET: u8 = 2;
163            ((self.bits >> OFFSET) & MASK as u32) as u8
164        };
165        ETR_ADC3_RMPR { bits }
166    }
167    #[doc = "Bit 4 - Input Capture 1 remap"]
168    #[inline]
169    pub fn ti1_rmp(&self) -> TI1_RMPR {
170        let bits = {
171            const MASK: bool = true;
172            const OFFSET: u8 = 4;
173            ((self.bits >> OFFSET) & MASK as u32) != 0
174        };
175        TI1_RMPR { bits }
176    }
177}
178impl W {
179    #[doc = r" Reset value of the register"]
180    #[inline]
181    pub fn reset_value() -> W {
182        W { bits: 0 }
183    }
184    #[doc = r" Writes raw bits to the register"]
185    #[inline]
186    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
187        self.bits = bits;
188        self
189    }
190    #[doc = "Bits 0:1 - External trigger remap on ADC1 analog watchdog"]
191    #[inline]
192    pub fn etr_adc1_rmp(&mut self) -> _ETR_ADC1_RMPW {
193        _ETR_ADC1_RMPW { w: self }
194    }
195    #[doc = "Bits 2:3 - External trigger remap on ADC3 analog watchdog"]
196    #[inline]
197    pub fn etr_adc3_rmp(&mut self) -> _ETR_ADC3_RMPW {
198        _ETR_ADC3_RMPW { w: self }
199    }
200    #[doc = "Bit 4 - Input Capture 1 remap"]
201    #[inline]
202    pub fn ti1_rmp(&mut self) -> _TI1_RMPW {
203        _TI1_RMPW { w: self }
204    }
205}
stm32l4x2_pac/tim1/or1.rs

stm32l4x2_pac/tim1/
or1.rs
