1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::CR1 {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = r" Value of the field"]
46pub struct CKDR {
47 bits: u8,
48}
49impl CKDR {
50 #[doc = r" Value of the field as raw bits"]
51 #[inline]
52 pub fn bits(&self) -> u8 {
53 self.bits
54 }
55}
56#[doc = "Possible values of the field `ARPE`"]
57#[derive(Clone, Copy, Debug, PartialEq)]
58pub enum ARPER {
59 #[doc = "TIMx_APRR register is not buffered"]
60 DISABLED,
61 #[doc = "TIMx_APRR register is buffered"]
62 ENABLED,
63}
64impl ARPER {
65 #[doc = r" Returns `true` if the bit is clear (0)"]
66 #[inline]
67 pub fn bit_is_clear(&self) -> bool {
68 !self.bit()
69 }
70 #[doc = r" Returns `true` if the bit is set (1)"]
71 #[inline]
72 pub fn bit_is_set(&self) -> bool {
73 self.bit()
74 }
75 #[doc = r" Value of the field as raw bits"]
76 #[inline]
77 pub fn bit(&self) -> bool {
78 match *self {
79 ARPER::DISABLED => false,
80 ARPER::ENABLED => true,
81 }
82 }
83 #[allow(missing_docs)]
84 #[doc(hidden)]
85 #[inline]
86 pub fn _from(value: bool) -> ARPER {
87 match value {
88 false => ARPER::DISABLED,
89 true => ARPER::ENABLED,
90 }
91 }
92 #[doc = "Checks if the value of the field is `DISABLED`"]
93 #[inline]
94 pub fn is_disabled(&self) -> bool {
95 *self == ARPER::DISABLED
96 }
97 #[doc = "Checks if the value of the field is `ENABLED`"]
98 #[inline]
99 pub fn is_enabled(&self) -> bool {
100 *self == ARPER::ENABLED
101 }
102}
103#[doc = r" Value of the field"]
104pub struct CMSR {
105 bits: u8,
106}
107impl CMSR {
108 #[doc = r" Value of the field as raw bits"]
109 #[inline]
110 pub fn bits(&self) -> u8 {
111 self.bits
112 }
113}
114#[doc = r" Value of the field"]
115pub struct DIRR {
116 bits: bool,
117}
118impl DIRR {
119 #[doc = r" Value of the field as raw bits"]
120 #[inline]
121 pub fn bit(&self) -> bool {
122 self.bits
123 }
124 #[doc = r" Returns `true` if the bit is clear (0)"]
125 #[inline]
126 pub fn bit_is_clear(&self) -> bool {
127 !self.bit()
128 }
129 #[doc = r" Returns `true` if the bit is set (1)"]
130 #[inline]
131 pub fn bit_is_set(&self) -> bool {
132 self.bit()
133 }
134}
135#[doc = "Possible values of the field `OPM`"]
136#[derive(Clone, Copy, Debug, PartialEq)]
137pub enum OPMR {
138 #[doc = "Counter is not stopped at update event"]
139 DISABLED,
140 #[doc = "Counter stops counting at the next update event (clearing the CEN bit)"]
141 ENABLED,
142}
143impl OPMR {
144 #[doc = r" Returns `true` if the bit is clear (0)"]
145 #[inline]
146 pub fn bit_is_clear(&self) -> bool {
147 !self.bit()
148 }
149 #[doc = r" Returns `true` if the bit is set (1)"]
150 #[inline]
151 pub fn bit_is_set(&self) -> bool {
152 self.bit()
153 }
154 #[doc = r" Value of the field as raw bits"]
155 #[inline]
156 pub fn bit(&self) -> bool {
157 match *self {
158 OPMR::DISABLED => false,
159 OPMR::ENABLED => true,
160 }
161 }
162 #[allow(missing_docs)]
163 #[doc(hidden)]
164 #[inline]
165 pub fn _from(value: bool) -> OPMR {
166 match value {
167 false => OPMR::DISABLED,
168 true => OPMR::ENABLED,
169 }
170 }
171 #[doc = "Checks if the value of the field is `DISABLED`"]
172 #[inline]
173 pub fn is_disabled(&self) -> bool {
174 *self == OPMR::DISABLED
175 }
176 #[doc = "Checks if the value of the field is `ENABLED`"]
177 #[inline]
178 pub fn is_enabled(&self) -> bool {
179 *self == OPMR::ENABLED
180 }
181}
182#[doc = "Possible values of the field `URS`"]
183#[derive(Clone, Copy, Debug, PartialEq)]
184pub enum URSR {
185 #[doc = "Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request"]
186 ANYEVENT,
187 #[doc = "Only counter overflow/underflow generates an update interrupt or DMA request"]
188 COUNTERONLY,
189}
190impl URSR {
191 #[doc = r" Returns `true` if the bit is clear (0)"]
192 #[inline]
193 pub fn bit_is_clear(&self) -> bool {
194 !self.bit()
195 }
196 #[doc = r" Returns `true` if the bit is set (1)"]
197 #[inline]
198 pub fn bit_is_set(&self) -> bool {
199 self.bit()
200 }
201 #[doc = r" Value of the field as raw bits"]
202 #[inline]
203 pub fn bit(&self) -> bool {
204 match *self {
205 URSR::ANYEVENT => false,
206 URSR::COUNTERONLY => true,
207 }
208 }
209 #[allow(missing_docs)]
210 #[doc(hidden)]
211 #[inline]
212 pub fn _from(value: bool) -> URSR {
213 match value {
214 false => URSR::ANYEVENT,
215 true => URSR::COUNTERONLY,
216 }
217 }
218 #[doc = "Checks if the value of the field is `ANYEVENT`"]
219 #[inline]
220 pub fn is_any_event(&self) -> bool {
221 *self == URSR::ANYEVENT
222 }
223 #[doc = "Checks if the value of the field is `COUNTERONLY`"]
224 #[inline]
225 pub fn is_counter_only(&self) -> bool {
226 *self == URSR::COUNTERONLY
227 }
228}
229#[doc = "Possible values of the field `UDIS`"]
230#[derive(Clone, Copy, Debug, PartialEq)]
231pub enum UDISR {
232 #[doc = "Update event enabled"]
233 ENABLED,
234 #[doc = "Update event disabled"]
235 DISABLED,
236}
237impl UDISR {
238 #[doc = r" Returns `true` if the bit is clear (0)"]
239 #[inline]
240 pub fn bit_is_clear(&self) -> bool {
241 !self.bit()
242 }
243 #[doc = r" Returns `true` if the bit is set (1)"]
244 #[inline]
245 pub fn bit_is_set(&self) -> bool {
246 self.bit()
247 }
248 #[doc = r" Value of the field as raw bits"]
249 #[inline]
250 pub fn bit(&self) -> bool {
251 match *self {
252 UDISR::ENABLED => false,
253 UDISR::DISABLED => true,
254 }
255 }
256 #[allow(missing_docs)]
257 #[doc(hidden)]
258 #[inline]
259 pub fn _from(value: bool) -> UDISR {
260 match value {
261 false => UDISR::ENABLED,
262 true => UDISR::DISABLED,
263 }
264 }
265 #[doc = "Checks if the value of the field is `ENABLED`"]
266 #[inline]
267 pub fn is_enabled(&self) -> bool {
268 *self == UDISR::ENABLED
269 }
270 #[doc = "Checks if the value of the field is `DISABLED`"]
271 #[inline]
272 pub fn is_disabled(&self) -> bool {
273 *self == UDISR::DISABLED
274 }
275}
276#[doc = "Possible values of the field `CEN`"]
277#[derive(Clone, Copy, Debug, PartialEq)]
278pub enum CENR {
279 #[doc = "Counter disabled"]
280 DISABLED,
281 #[doc = "Counter enabled"]
282 ENABLED,
283}
284impl CENR {
285 #[doc = r" Returns `true` if the bit is clear (0)"]
286 #[inline]
287 pub fn bit_is_clear(&self) -> bool {
288 !self.bit()
289 }
290 #[doc = r" Returns `true` if the bit is set (1)"]
291 #[inline]
292 pub fn bit_is_set(&self) -> bool {
293 self.bit()
294 }
295 #[doc = r" Value of the field as raw bits"]
296 #[inline]
297 pub fn bit(&self) -> bool {
298 match *self {
299 CENR::DISABLED => false,
300 CENR::ENABLED => true,
301 }
302 }
303 #[allow(missing_docs)]
304 #[doc(hidden)]
305 #[inline]
306 pub fn _from(value: bool) -> CENR {
307 match value {
308 false => CENR::DISABLED,
309 true => CENR::ENABLED,
310 }
311 }
312 #[doc = "Checks if the value of the field is `DISABLED`"]
313 #[inline]
314 pub fn is_disabled(&self) -> bool {
315 *self == CENR::DISABLED
316 }
317 #[doc = "Checks if the value of the field is `ENABLED`"]
318 #[inline]
319 pub fn is_enabled(&self) -> bool {
320 *self == CENR::ENABLED
321 }
322}
323#[doc = r" Proxy"]
324pub struct _CKDW<'a> {
325 w: &'a mut W,
326}
327impl<'a> _CKDW<'a> {
328 #[doc = r" Writes raw bits to the field"]
329 #[inline]
330 pub unsafe fn bits(self, value: u8) -> &'a mut W {
331 const MASK: u8 = 3;
332 const OFFSET: u8 = 8;
333 self.w.bits &= !((MASK as u32) << OFFSET);
334 self.w.bits |= ((value & MASK) as u32) << OFFSET;
335 self.w
336 }
337}
338#[doc = "Values that can be written to the field `ARPE`"]
339pub enum ARPEW {
340 #[doc = "TIMx_APRR register is not buffered"]
341 DISABLED,
342 #[doc = "TIMx_APRR register is buffered"]
343 ENABLED,
344}
345impl ARPEW {
346 #[allow(missing_docs)]
347 #[doc(hidden)]
348 #[inline]
349 pub fn _bits(&self) -> bool {
350 match *self {
351 ARPEW::DISABLED => false,
352 ARPEW::ENABLED => true,
353 }
354 }
355}
356#[doc = r" Proxy"]
357pub struct _ARPEW<'a> {
358 w: &'a mut W,
359}
360impl<'a> _ARPEW<'a> {
361 #[doc = r" Writes `variant` to the field"]
362 #[inline]
363 pub fn variant(self, variant: ARPEW) -> &'a mut W {
364 {
365 self.bit(variant._bits())
366 }
367 }
368 #[doc = "TIMx_APRR register is not buffered"]
369 #[inline]
370 pub fn disabled(self) -> &'a mut W {
371 self.variant(ARPEW::DISABLED)
372 }
373 #[doc = "TIMx_APRR register is buffered"]
374 #[inline]
375 pub fn enabled(self) -> &'a mut W {
376 self.variant(ARPEW::ENABLED)
377 }
378 #[doc = r" Sets the field bit"]
379 pub fn set_bit(self) -> &'a mut W {
380 self.bit(true)
381 }
382 #[doc = r" Clears the field bit"]
383 pub fn clear_bit(self) -> &'a mut W {
384 self.bit(false)
385 }
386 #[doc = r" Writes raw bits to the field"]
387 #[inline]
388 pub fn bit(self, value: bool) -> &'a mut W {
389 const MASK: bool = true;
390 const OFFSET: u8 = 7;
391 self.w.bits &= !((MASK as u32) << OFFSET);
392 self.w.bits |= ((value & MASK) as u32) << OFFSET;
393 self.w
394 }
395}
396#[doc = r" Proxy"]
397pub struct _CMSW<'a> {
398 w: &'a mut W,
399}
400impl<'a> _CMSW<'a> {
401 #[doc = r" Writes raw bits to the field"]
402 #[inline]
403 pub unsafe fn bits(self, value: u8) -> &'a mut W {
404 const MASK: u8 = 3;
405 const OFFSET: u8 = 5;
406 self.w.bits &= !((MASK as u32) << OFFSET);
407 self.w.bits |= ((value & MASK) as u32) << OFFSET;
408 self.w
409 }
410}
411#[doc = r" Proxy"]
412pub struct _DIRW<'a> {
413 w: &'a mut W,
414}
415impl<'a> _DIRW<'a> {
416 #[doc = r" Sets the field bit"]
417 pub fn set_bit(self) -> &'a mut W {
418 self.bit(true)
419 }
420 #[doc = r" Clears the field bit"]
421 pub fn clear_bit(self) -> &'a mut W {
422 self.bit(false)
423 }
424 #[doc = r" Writes raw bits to the field"]
425 #[inline]
426 pub fn bit(self, value: bool) -> &'a mut W {
427 const MASK: bool = true;
428 const OFFSET: u8 = 4;
429 self.w.bits &= !((MASK as u32) << OFFSET);
430 self.w.bits |= ((value & MASK) as u32) << OFFSET;
431 self.w
432 }
433}
434#[doc = "Values that can be written to the field `OPM`"]
435pub enum OPMW {
436 #[doc = "Counter is not stopped at update event"]
437 DISABLED,
438 #[doc = "Counter stops counting at the next update event (clearing the CEN bit)"]
439 ENABLED,
440}
441impl OPMW {
442 #[allow(missing_docs)]
443 #[doc(hidden)]
444 #[inline]
445 pub fn _bits(&self) -> bool {
446 match *self {
447 OPMW::DISABLED => false,
448 OPMW::ENABLED => true,
449 }
450 }
451}
452#[doc = r" Proxy"]
453pub struct _OPMW<'a> {
454 w: &'a mut W,
455}
456impl<'a> _OPMW<'a> {
457 #[doc = r" Writes `variant` to the field"]
458 #[inline]
459 pub fn variant(self, variant: OPMW) -> &'a mut W {
460 {
461 self.bit(variant._bits())
462 }
463 }
464 #[doc = "Counter is not stopped at update event"]
465 #[inline]
466 pub fn disabled(self) -> &'a mut W {
467 self.variant(OPMW::DISABLED)
468 }
469 #[doc = "Counter stops counting at the next update event (clearing the CEN bit)"]
470 #[inline]
471 pub fn enabled(self) -> &'a mut W {
472 self.variant(OPMW::ENABLED)
473 }
474 #[doc = r" Sets the field bit"]
475 pub fn set_bit(self) -> &'a mut W {
476 self.bit(true)
477 }
478 #[doc = r" Clears the field bit"]
479 pub fn clear_bit(self) -> &'a mut W {
480 self.bit(false)
481 }
482 #[doc = r" Writes raw bits to the field"]
483 #[inline]
484 pub fn bit(self, value: bool) -> &'a mut W {
485 const MASK: bool = true;
486 const OFFSET: u8 = 3;
487 self.w.bits &= !((MASK as u32) << OFFSET);
488 self.w.bits |= ((value & MASK) as u32) << OFFSET;
489 self.w
490 }
491}
492#[doc = "Values that can be written to the field `URS`"]
493pub enum URSW {
494 #[doc = "Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request"]
495 ANYEVENT,
496 #[doc = "Only counter overflow/underflow generates an update interrupt or DMA request"]
497 COUNTERONLY,
498}
499impl URSW {
500 #[allow(missing_docs)]
501 #[doc(hidden)]
502 #[inline]
503 pub fn _bits(&self) -> bool {
504 match *self {
505 URSW::ANYEVENT => false,
506 URSW::COUNTERONLY => true,
507 }
508 }
509}
510#[doc = r" Proxy"]
511pub struct _URSW<'a> {
512 w: &'a mut W,
513}
514impl<'a> _URSW<'a> {
515 #[doc = r" Writes `variant` to the field"]
516 #[inline]
517 pub fn variant(self, variant: URSW) -> &'a mut W {
518 {
519 self.bit(variant._bits())
520 }
521 }
522 #[doc = "Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request"]
523 #[inline]
524 pub fn any_event(self) -> &'a mut W {
525 self.variant(URSW::ANYEVENT)
526 }
527 #[doc = "Only counter overflow/underflow generates an update interrupt or DMA request"]
528 #[inline]
529 pub fn counter_only(self) -> &'a mut W {
530 self.variant(URSW::COUNTERONLY)
531 }
532 #[doc = r" Sets the field bit"]
533 pub fn set_bit(self) -> &'a mut W {
534 self.bit(true)
535 }
536 #[doc = r" Clears the field bit"]
537 pub fn clear_bit(self) -> &'a mut W {
538 self.bit(false)
539 }
540 #[doc = r" Writes raw bits to the field"]
541 #[inline]
542 pub fn bit(self, value: bool) -> &'a mut W {
543 const MASK: bool = true;
544 const OFFSET: u8 = 2;
545 self.w.bits &= !((MASK as u32) << OFFSET);
546 self.w.bits |= ((value & MASK) as u32) << OFFSET;
547 self.w
548 }
549}
550#[doc = "Values that can be written to the field `UDIS`"]
551pub enum UDISW {
552 #[doc = "Update event enabled"]
553 ENABLED,
554 #[doc = "Update event disabled"]
555 DISABLED,
556}
557impl UDISW {
558 #[allow(missing_docs)]
559 #[doc(hidden)]
560 #[inline]
561 pub fn _bits(&self) -> bool {
562 match *self {
563 UDISW::ENABLED => false,
564 UDISW::DISABLED => true,
565 }
566 }
567}
568#[doc = r" Proxy"]
569pub struct _UDISW<'a> {
570 w: &'a mut W,
571}
572impl<'a> _UDISW<'a> {
573 #[doc = r" Writes `variant` to the field"]
574 #[inline]
575 pub fn variant(self, variant: UDISW) -> &'a mut W {
576 {
577 self.bit(variant._bits())
578 }
579 }
580 #[doc = "Update event enabled"]
581 #[inline]
582 pub fn enabled(self) -> &'a mut W {
583 self.variant(UDISW::ENABLED)
584 }
585 #[doc = "Update event disabled"]
586 #[inline]
587 pub fn disabled(self) -> &'a mut W {
588 self.variant(UDISW::DISABLED)
589 }
590 #[doc = r" Sets the field bit"]
591 pub fn set_bit(self) -> &'a mut W {
592 self.bit(true)
593 }
594 #[doc = r" Clears the field bit"]
595 pub fn clear_bit(self) -> &'a mut W {
596 self.bit(false)
597 }
598 #[doc = r" Writes raw bits to the field"]
599 #[inline]
600 pub fn bit(self, value: bool) -> &'a mut W {
601 const MASK: bool = true;
602 const OFFSET: u8 = 1;
603 self.w.bits &= !((MASK as u32) << OFFSET);
604 self.w.bits |= ((value & MASK) as u32) << OFFSET;
605 self.w
606 }
607}
608#[doc = "Values that can be written to the field `CEN`"]
609pub enum CENW {
610 #[doc = "Counter disabled"]
611 DISABLED,
612 #[doc = "Counter enabled"]
613 ENABLED,
614}
615impl CENW {
616 #[allow(missing_docs)]
617 #[doc(hidden)]
618 #[inline]
619 pub fn _bits(&self) -> bool {
620 match *self {
621 CENW::DISABLED => false,
622 CENW::ENABLED => true,
623 }
624 }
625}
626#[doc = r" Proxy"]
627pub struct _CENW<'a> {
628 w: &'a mut W,
629}
630impl<'a> _CENW<'a> {
631 #[doc = r" Writes `variant` to the field"]
632 #[inline]
633 pub fn variant(self, variant: CENW) -> &'a mut W {
634 {
635 self.bit(variant._bits())
636 }
637 }
638 #[doc = "Counter disabled"]
639 #[inline]
640 pub fn disabled(self) -> &'a mut W {
641 self.variant(CENW::DISABLED)
642 }
643 #[doc = "Counter enabled"]
644 #[inline]
645 pub fn enabled(self) -> &'a mut W {
646 self.variant(CENW::ENABLED)
647 }
648 #[doc = r" Sets the field bit"]
649 pub fn set_bit(self) -> &'a mut W {
650 self.bit(true)
651 }
652 #[doc = r" Clears the field bit"]
653 pub fn clear_bit(self) -> &'a mut W {
654 self.bit(false)
655 }
656 #[doc = r" Writes raw bits to the field"]
657 #[inline]
658 pub fn bit(self, value: bool) -> &'a mut W {
659 const MASK: bool = true;
660 const OFFSET: u8 = 0;
661 self.w.bits &= !((MASK as u32) << OFFSET);
662 self.w.bits |= ((value & MASK) as u32) << OFFSET;
663 self.w
664 }
665}
666impl R {
667 #[doc = r" Value of the register as raw bits"]
668 #[inline]
669 pub fn bits(&self) -> u32 {
670 self.bits
671 }
672 #[doc = "Bits 8:9 - Clock division"]
673 #[inline]
674 pub fn ckd(&self) -> CKDR {
675 let bits = {
676 const MASK: u8 = 3;
677 const OFFSET: u8 = 8;
678 ((self.bits >> OFFSET) & MASK as u32) as u8
679 };
680 CKDR { bits }
681 }
682 #[doc = "Bit 7 - Auto-reload preload enable"]
683 #[inline]
684 pub fn arpe(&self) -> ARPER {
685 ARPER::_from({
686 const MASK: bool = true;
687 const OFFSET: u8 = 7;
688 ((self.bits >> OFFSET) & MASK as u32) != 0
689 })
690 }
691 #[doc = "Bits 5:6 - Center-aligned mode selection"]
692 #[inline]
693 pub fn cms(&self) -> CMSR {
694 let bits = {
695 const MASK: u8 = 3;
696 const OFFSET: u8 = 5;
697 ((self.bits >> OFFSET) & MASK as u32) as u8
698 };
699 CMSR { bits }
700 }
701 #[doc = "Bit 4 - Direction"]
702 #[inline]
703 pub fn dir(&self) -> DIRR {
704 let bits = {
705 const MASK: bool = true;
706 const OFFSET: u8 = 4;
707 ((self.bits >> OFFSET) & MASK as u32) != 0
708 };
709 DIRR { bits }
710 }
711 #[doc = "Bit 3 - One-pulse mode"]
712 #[inline]
713 pub fn opm(&self) -> OPMR {
714 OPMR::_from({
715 const MASK: bool = true;
716 const OFFSET: u8 = 3;
717 ((self.bits >> OFFSET) & MASK as u32) != 0
718 })
719 }
720 #[doc = "Bit 2 - Update request source"]
721 #[inline]
722 pub fn urs(&self) -> URSR {
723 URSR::_from({
724 const MASK: bool = true;
725 const OFFSET: u8 = 2;
726 ((self.bits >> OFFSET) & MASK as u32) != 0
727 })
728 }
729 #[doc = "Bit 1 - Update disable"]
730 #[inline]
731 pub fn udis(&self) -> UDISR {
732 UDISR::_from({
733 const MASK: bool = true;
734 const OFFSET: u8 = 1;
735 ((self.bits >> OFFSET) & MASK as u32) != 0
736 })
737 }
738 #[doc = "Bit 0 - Counter enable"]
739 #[inline]
740 pub fn cen(&self) -> CENR {
741 CENR::_from({
742 const MASK: bool = true;
743 const OFFSET: u8 = 0;
744 ((self.bits >> OFFSET) & MASK as u32) != 0
745 })
746 }
747}
748impl W {
749 #[doc = r" Reset value of the register"]
750 #[inline]
751 pub fn reset_value() -> W {
752 W { bits: 0 }
753 }
754 #[doc = r" Writes raw bits to the register"]
755 #[inline]
756 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
757 self.bits = bits;
758 self
759 }
760 #[doc = "Bits 8:9 - Clock division"]
761 #[inline]
762 pub fn ckd(&mut self) -> _CKDW {
763 _CKDW { w: self }
764 }
765 #[doc = "Bit 7 - Auto-reload preload enable"]
766 #[inline]
767 pub fn arpe(&mut self) -> _ARPEW {
768 _ARPEW { w: self }
769 }
770 #[doc = "Bits 5:6 - Center-aligned mode selection"]
771 #[inline]
772 pub fn cms(&mut self) -> _CMSW {
773 _CMSW { w: self }
774 }
775 #[doc = "Bit 4 - Direction"]
776 #[inline]
777 pub fn dir(&mut self) -> _DIRW {
778 _DIRW { w: self }
779 }
780 #[doc = "Bit 3 - One-pulse mode"]
781 #[inline]
782 pub fn opm(&mut self) -> _OPMW {
783 _OPMW { w: self }
784 }
785 #[doc = "Bit 2 - Update request source"]
786 #[inline]
787 pub fn urs(&mut self) -> _URSW {
788 _URSW { w: self }
789 }
790 #[doc = "Bit 1 - Update disable"]
791 #[inline]
792 pub fn udis(&mut self) -> _UDISW {
793 _UDISW { w: self }
794 }
795 #[doc = "Bit 0 - Counter enable"]
796 #[inline]
797 pub fn cen(&mut self) -> _CENW {
798 _CENW { w: self }
799 }
800}