stm32l4x2_pac/syscfg/
scsr.rs

1#[doc = r" Value read from the register"]
2pub struct R {
3    bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7    bits: u32,
8}
9impl super::SCSR {
10    #[doc = r" Modifies the contents of the register"]
11    #[inline]
12    pub fn modify<F>(&self, f: F)
13    where
14        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15    {
16        let bits = self.register.get();
17        let r = R { bits: bits };
18        let mut w = W { bits: bits };
19        f(&r, &mut w);
20        self.register.set(w.bits);
21    }
22    #[doc = r" Reads the contents of the register"]
23    #[inline]
24    pub fn read(&self) -> R {
25        R {
26            bits: self.register.get(),
27        }
28    }
29    #[doc = r" Writes to the register"]
30    #[inline]
31    pub fn write<F>(&self, f: F)
32    where
33        F: FnOnce(&mut W) -> &mut W,
34    {
35        let mut w = W::reset_value();
36        f(&mut w);
37        self.register.set(w.bits);
38    }
39    #[doc = r" Writes the reset value to the register"]
40    #[inline]
41    pub fn reset(&self) {
42        self.write(|w| w)
43    }
44}
45#[doc = r" Value of the field"]
46pub struct SRAM2BSYR {
47    bits: bool,
48}
49impl SRAM2BSYR {
50    #[doc = r" Value of the field as raw bits"]
51    #[inline]
52    pub fn bit(&self) -> bool {
53        self.bits
54    }
55    #[doc = r" Returns `true` if the bit is clear (0)"]
56    #[inline]
57    pub fn bit_is_clear(&self) -> bool {
58        !self.bit()
59    }
60    #[doc = r" Returns `true` if the bit is set (1)"]
61    #[inline]
62    pub fn bit_is_set(&self) -> bool {
63        self.bit()
64    }
65}
66#[doc = r" Value of the field"]
67pub struct SRAM2ERR {
68    bits: bool,
69}
70impl SRAM2ERR {
71    #[doc = r" Value of the field as raw bits"]
72    #[inline]
73    pub fn bit(&self) -> bool {
74        self.bits
75    }
76    #[doc = r" Returns `true` if the bit is clear (0)"]
77    #[inline]
78    pub fn bit_is_clear(&self) -> bool {
79        !self.bit()
80    }
81    #[doc = r" Returns `true` if the bit is set (1)"]
82    #[inline]
83    pub fn bit_is_set(&self) -> bool {
84        self.bit()
85    }
86}
87#[doc = r" Proxy"]
88pub struct _SRAM2ERW<'a> {
89    w: &'a mut W,
90}
91impl<'a> _SRAM2ERW<'a> {
92    #[doc = r" Sets the field bit"]
93    pub fn set_bit(self) -> &'a mut W {
94        self.bit(true)
95    }
96    #[doc = r" Clears the field bit"]
97    pub fn clear_bit(self) -> &'a mut W {
98        self.bit(false)
99    }
100    #[doc = r" Writes raw bits to the field"]
101    #[inline]
102    pub fn bit(self, value: bool) -> &'a mut W {
103        const MASK: bool = true;
104        const OFFSET: u8 = 0;
105        self.w.bits &= !((MASK as u32) << OFFSET);
106        self.w.bits |= ((value & MASK) as u32) << OFFSET;
107        self.w
108    }
109}
110impl R {
111    #[doc = r" Value of the register as raw bits"]
112    #[inline]
113    pub fn bits(&self) -> u32 {
114        self.bits
115    }
116    #[doc = "Bit 1 - SRAM2 busy by erase operation"]
117    #[inline]
118    pub fn sram2bsy(&self) -> SRAM2BSYR {
119        let bits = {
120            const MASK: bool = true;
121            const OFFSET: u8 = 1;
122            ((self.bits >> OFFSET) & MASK as u32) != 0
123        };
124        SRAM2BSYR { bits }
125    }
126    #[doc = "Bit 0 - SRAM2 Erase"]
127    #[inline]
128    pub fn sram2er(&self) -> SRAM2ERR {
129        let bits = {
130            const MASK: bool = true;
131            const OFFSET: u8 = 0;
132            ((self.bits >> OFFSET) & MASK as u32) != 0
133        };
134        SRAM2ERR { bits }
135    }
136}
137impl W {
138    #[doc = r" Reset value of the register"]
139    #[inline]
140    pub fn reset_value() -> W {
141        W { bits: 0 }
142    }
143    #[doc = r" Writes raw bits to the register"]
144    #[inline]
145    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
146        self.bits = bits;
147        self
148    }
149    #[doc = "Bit 0 - SRAM2 Erase"]
150    #[inline]
151    pub fn sram2er(&mut self) -> _SRAM2ERW {
152        _SRAM2ERW { w: self }
153    }
154}
stm32l4x2_pac/syscfg/scsr.rs

stm32l4x2_pac/syscfg/
scsr.rs
