stm32l4x2_pac/syscfg/
memrmp.rs

1#[doc = r" Value read from the register"]
2pub struct R {
3    bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7    bits: u32,
8}
9impl super::MEMRMP {
10    #[doc = r" Modifies the contents of the register"]
11    #[inline]
12    pub fn modify<F>(&self, f: F)
13    where
14        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15    {
16        let bits = self.register.get();
17        let r = R { bits: bits };
18        let mut w = W { bits: bits };
19        f(&r, &mut w);
20        self.register.set(w.bits);
21    }
22    #[doc = r" Reads the contents of the register"]
23    #[inline]
24    pub fn read(&self) -> R {
25        R {
26            bits: self.register.get(),
27        }
28    }
29    #[doc = r" Writes to the register"]
30    #[inline]
31    pub fn write<F>(&self, f: F)
32    where
33        F: FnOnce(&mut W) -> &mut W,
34    {
35        let mut w = W::reset_value();
36        f(&mut w);
37        self.register.set(w.bits);
38    }
39    #[doc = r" Writes the reset value to the register"]
40    #[inline]
41    pub fn reset(&self) {
42        self.write(|w| w)
43    }
44}
45#[doc = r" Value of the field"]
46pub struct FB_MODER {
47    bits: bool,
48}
49impl FB_MODER {
50    #[doc = r" Value of the field as raw bits"]
51    #[inline]
52    pub fn bit(&self) -> bool {
53        self.bits
54    }
55    #[doc = r" Returns `true` if the bit is clear (0)"]
56    #[inline]
57    pub fn bit_is_clear(&self) -> bool {
58        !self.bit()
59    }
60    #[doc = r" Returns `true` if the bit is set (1)"]
61    #[inline]
62    pub fn bit_is_set(&self) -> bool {
63        self.bit()
64    }
65}
66#[doc = r" Value of the field"]
67pub struct QFSR {
68    bits: bool,
69}
70impl QFSR {
71    #[doc = r" Value of the field as raw bits"]
72    #[inline]
73    pub fn bit(&self) -> bool {
74        self.bits
75    }
76    #[doc = r" Returns `true` if the bit is clear (0)"]
77    #[inline]
78    pub fn bit_is_clear(&self) -> bool {
79        !self.bit()
80    }
81    #[doc = r" Returns `true` if the bit is set (1)"]
82    #[inline]
83    pub fn bit_is_set(&self) -> bool {
84        self.bit()
85    }
86}
87#[doc = r" Value of the field"]
88pub struct MEM_MODER {
89    bits: u8,
90}
91impl MEM_MODER {
92    #[doc = r" Value of the field as raw bits"]
93    #[inline]
94    pub fn bits(&self) -> u8 {
95        self.bits
96    }
97}
98#[doc = r" Proxy"]
99pub struct _FB_MODEW<'a> {
100    w: &'a mut W,
101}
102impl<'a> _FB_MODEW<'a> {
103    #[doc = r" Sets the field bit"]
104    pub fn set_bit(self) -> &'a mut W {
105        self.bit(true)
106    }
107    #[doc = r" Clears the field bit"]
108    pub fn clear_bit(self) -> &'a mut W {
109        self.bit(false)
110    }
111    #[doc = r" Writes raw bits to the field"]
112    #[inline]
113    pub fn bit(self, value: bool) -> &'a mut W {
114        const MASK: bool = true;
115        const OFFSET: u8 = 8;
116        self.w.bits &= !((MASK as u32) << OFFSET);
117        self.w.bits |= ((value & MASK) as u32) << OFFSET;
118        self.w
119    }
120}
121#[doc = r" Proxy"]
122pub struct _QFSW<'a> {
123    w: &'a mut W,
124}
125impl<'a> _QFSW<'a> {
126    #[doc = r" Sets the field bit"]
127    pub fn set_bit(self) -> &'a mut W {
128        self.bit(true)
129    }
130    #[doc = r" Clears the field bit"]
131    pub fn clear_bit(self) -> &'a mut W {
132        self.bit(false)
133    }
134    #[doc = r" Writes raw bits to the field"]
135    #[inline]
136    pub fn bit(self, value: bool) -> &'a mut W {
137        const MASK: bool = true;
138        const OFFSET: u8 = 3;
139        self.w.bits &= !((MASK as u32) << OFFSET);
140        self.w.bits |= ((value & MASK) as u32) << OFFSET;
141        self.w
142    }
143}
144#[doc = r" Proxy"]
145pub struct _MEM_MODEW<'a> {
146    w: &'a mut W,
147}
148impl<'a> _MEM_MODEW<'a> {
149    #[doc = r" Writes raw bits to the field"]
150    #[inline]
151    pub unsafe fn bits(self, value: u8) -> &'a mut W {
152        const MASK: u8 = 7;
153        const OFFSET: u8 = 0;
154        self.w.bits &= !((MASK as u32) << OFFSET);
155        self.w.bits |= ((value & MASK) as u32) << OFFSET;
156        self.w
157    }
158}
159impl R {
160    #[doc = r" Value of the register as raw bits"]
161    #[inline]
162    pub fn bits(&self) -> u32 {
163        self.bits
164    }
165    #[doc = "Bit 8 - Flash Bank mode selection"]
166    #[inline]
167    pub fn fb_mode(&self) -> FB_MODER {
168        let bits = {
169            const MASK: bool = true;
170            const OFFSET: u8 = 8;
171            ((self.bits >> OFFSET) & MASK as u32) != 0
172        };
173        FB_MODER { bits }
174    }
175    #[doc = "Bit 3 - QUADSPI memory mapping swap"]
176    #[inline]
177    pub fn qfs(&self) -> QFSR {
178        let bits = {
179            const MASK: bool = true;
180            const OFFSET: u8 = 3;
181            ((self.bits >> OFFSET) & MASK as u32) != 0
182        };
183        QFSR { bits }
184    }
185    #[doc = "Bits 0:2 - Memory mapping selection"]
186    #[inline]
187    pub fn mem_mode(&self) -> MEM_MODER {
188        let bits = {
189            const MASK: u8 = 7;
190            const OFFSET: u8 = 0;
191            ((self.bits >> OFFSET) & MASK as u32) as u8
192        };
193        MEM_MODER { bits }
194    }
195}
196impl W {
197    #[doc = r" Reset value of the register"]
198    #[inline]
199    pub fn reset_value() -> W {
200        W { bits: 0 }
201    }
202    #[doc = r" Writes raw bits to the register"]
203    #[inline]
204    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
205        self.bits = bits;
206        self
207    }
208    #[doc = "Bit 8 - Flash Bank mode selection"]
209    #[inline]
210    pub fn fb_mode(&mut self) -> _FB_MODEW {
211        _FB_MODEW { w: self }
212    }
213    #[doc = "Bit 3 - QUADSPI memory mapping swap"]
214    #[inline]
215    pub fn qfs(&mut self) -> _QFSW {
216        _QFSW { w: self }
217    }
218    #[doc = "Bits 0:2 - Memory mapping selection"]
219    #[inline]
220    pub fn mem_mode(&mut self) -> _MEM_MODEW {
221        _MEM_MODEW { w: self }
222    }
223}
stm32l4x2_pac/syscfg/memrmp.rs

stm32l4x2_pac/syscfg/
memrmp.rs
