stm32l4x2_pac/syscfg/
cfgr2.rs

1#[doc = r" Value read from the register"]
2pub struct R {
3    bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7    bits: u32,
8}
9impl super::CFGR2 {
10    #[doc = r" Modifies the contents of the register"]
11    #[inline]
12    pub fn modify<F>(&self, f: F)
13    where
14        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15    {
16        let bits = self.register.get();
17        let r = R { bits: bits };
18        let mut w = W { bits: bits };
19        f(&r, &mut w);
20        self.register.set(w.bits);
21    }
22    #[doc = r" Reads the contents of the register"]
23    #[inline]
24    pub fn read(&self) -> R {
25        R {
26            bits: self.register.get(),
27        }
28    }
29    #[doc = r" Writes to the register"]
30    #[inline]
31    pub fn write<F>(&self, f: F)
32    where
33        F: FnOnce(&mut W) -> &mut W,
34    {
35        let mut w = W::reset_value();
36        f(&mut w);
37        self.register.set(w.bits);
38    }
39    #[doc = r" Writes the reset value to the register"]
40    #[inline]
41    pub fn reset(&self) {
42        self.write(|w| w)
43    }
44}
45#[doc = r" Value of the field"]
46pub struct SPFR {
47    bits: bool,
48}
49impl SPFR {
50    #[doc = r" Value of the field as raw bits"]
51    #[inline]
52    pub fn bit(&self) -> bool {
53        self.bits
54    }
55    #[doc = r" Returns `true` if the bit is clear (0)"]
56    #[inline]
57    pub fn bit_is_clear(&self) -> bool {
58        !self.bit()
59    }
60    #[doc = r" Returns `true` if the bit is set (1)"]
61    #[inline]
62    pub fn bit_is_set(&self) -> bool {
63        self.bit()
64    }
65}
66#[doc = r" Proxy"]
67pub struct _SPFW<'a> {
68    w: &'a mut W,
69}
70impl<'a> _SPFW<'a> {
71    #[doc = r" Sets the field bit"]
72    pub fn set_bit(self) -> &'a mut W {
73        self.bit(true)
74    }
75    #[doc = r" Clears the field bit"]
76    pub fn clear_bit(self) -> &'a mut W {
77        self.bit(false)
78    }
79    #[doc = r" Writes raw bits to the field"]
80    #[inline]
81    pub fn bit(self, value: bool) -> &'a mut W {
82        const MASK: bool = true;
83        const OFFSET: u8 = 8;
84        self.w.bits &= !((MASK as u32) << OFFSET);
85        self.w.bits |= ((value & MASK) as u32) << OFFSET;
86        self.w
87    }
88}
89#[doc = r" Proxy"]
90pub struct _ECCLW<'a> {
91    w: &'a mut W,
92}
93impl<'a> _ECCLW<'a> {
94    #[doc = r" Sets the field bit"]
95    pub fn set_bit(self) -> &'a mut W {
96        self.bit(true)
97    }
98    #[doc = r" Clears the field bit"]
99    pub fn clear_bit(self) -> &'a mut W {
100        self.bit(false)
101    }
102    #[doc = r" Writes raw bits to the field"]
103    #[inline]
104    pub fn bit(self, value: bool) -> &'a mut W {
105        const MASK: bool = true;
106        const OFFSET: u8 = 3;
107        self.w.bits &= !((MASK as u32) << OFFSET);
108        self.w.bits |= ((value & MASK) as u32) << OFFSET;
109        self.w
110    }
111}
112#[doc = r" Proxy"]
113pub struct _PVDLW<'a> {
114    w: &'a mut W,
115}
116impl<'a> _PVDLW<'a> {
117    #[doc = r" Sets the field bit"]
118    pub fn set_bit(self) -> &'a mut W {
119        self.bit(true)
120    }
121    #[doc = r" Clears the field bit"]
122    pub fn clear_bit(self) -> &'a mut W {
123        self.bit(false)
124    }
125    #[doc = r" Writes raw bits to the field"]
126    #[inline]
127    pub fn bit(self, value: bool) -> &'a mut W {
128        const MASK: bool = true;
129        const OFFSET: u8 = 2;
130        self.w.bits &= !((MASK as u32) << OFFSET);
131        self.w.bits |= ((value & MASK) as u32) << OFFSET;
132        self.w
133    }
134}
135#[doc = r" Proxy"]
136pub struct _SPLW<'a> {
137    w: &'a mut W,
138}
139impl<'a> _SPLW<'a> {
140    #[doc = r" Sets the field bit"]
141    pub fn set_bit(self) -> &'a mut W {
142        self.bit(true)
143    }
144    #[doc = r" Clears the field bit"]
145    pub fn clear_bit(self) -> &'a mut W {
146        self.bit(false)
147    }
148    #[doc = r" Writes raw bits to the field"]
149    #[inline]
150    pub fn bit(self, value: bool) -> &'a mut W {
151        const MASK: bool = true;
152        const OFFSET: u8 = 1;
153        self.w.bits &= !((MASK as u32) << OFFSET);
154        self.w.bits |= ((value & MASK) as u32) << OFFSET;
155        self.w
156    }
157}
158#[doc = r" Proxy"]
159pub struct _CLLW<'a> {
160    w: &'a mut W,
161}
162impl<'a> _CLLW<'a> {
163    #[doc = r" Sets the field bit"]
164    pub fn set_bit(self) -> &'a mut W {
165        self.bit(true)
166    }
167    #[doc = r" Clears the field bit"]
168    pub fn clear_bit(self) -> &'a mut W {
169        self.bit(false)
170    }
171    #[doc = r" Writes raw bits to the field"]
172    #[inline]
173    pub fn bit(self, value: bool) -> &'a mut W {
174        const MASK: bool = true;
175        const OFFSET: u8 = 0;
176        self.w.bits &= !((MASK as u32) << OFFSET);
177        self.w.bits |= ((value & MASK) as u32) << OFFSET;
178        self.w
179    }
180}
181impl R {
182    #[doc = r" Value of the register as raw bits"]
183    #[inline]
184    pub fn bits(&self) -> u32 {
185        self.bits
186    }
187    #[doc = "Bit 8 - SRAM2 parity error flag"]
188    #[inline]
189    pub fn spf(&self) -> SPFR {
190        let bits = {
191            const MASK: bool = true;
192            const OFFSET: u8 = 8;
193            ((self.bits >> OFFSET) & MASK as u32) != 0
194        };
195        SPFR { bits }
196    }
197}
198impl W {
199    #[doc = r" Reset value of the register"]
200    #[inline]
201    pub fn reset_value() -> W {
202        W { bits: 0 }
203    }
204    #[doc = r" Writes raw bits to the register"]
205    #[inline]
206    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
207        self.bits = bits;
208        self
209    }
210    #[doc = "Bit 8 - SRAM2 parity error flag"]
211    #[inline]
212    pub fn spf(&mut self) -> _SPFW {
213        _SPFW { w: self }
214    }
215    #[doc = "Bit 3 - ECC Lock"]
216    #[inline]
217    pub fn eccl(&mut self) -> _ECCLW {
218        _ECCLW { w: self }
219    }
220    #[doc = "Bit 2 - PVD lock enable bit"]
221    #[inline]
222    pub fn pvdl(&mut self) -> _PVDLW {
223        _PVDLW { w: self }
224    }
225    #[doc = "Bit 1 - SRAM2 parity lock bit"]
226    #[inline]
227    pub fn spl(&mut self) -> _SPLW {
228        _SPLW { w: self }
229    }
230    #[doc = "Bit 0 - OCKUP (Hardfault) output enable bit"]
231    #[inline]
232    pub fn cll(&mut self) -> _CLLW {
233        _CLLW { w: self }
234    }
235}
stm32l4x2_pac/syscfg/cfgr2.rs

stm32l4x2_pac/syscfg/
cfgr2.rs
