stm32l4x2_pac/stk/
calib.rs

1#[doc = r" Value read from the register"]
2pub struct R {
3    bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7    bits: u32,
8}
9impl super::CALIB {
10    #[doc = r" Modifies the contents of the register"]
11    #[inline]
12    pub fn modify<F>(&self, f: F)
13    where
14        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15    {
16        let bits = self.register.get();
17        let r = R { bits: bits };
18        let mut w = W { bits: bits };
19        f(&r, &mut w);
20        self.register.set(w.bits);
21    }
22    #[doc = r" Reads the contents of the register"]
23    #[inline]
24    pub fn read(&self) -> R {
25        R {
26            bits: self.register.get(),
27        }
28    }
29    #[doc = r" Writes to the register"]
30    #[inline]
31    pub fn write<F>(&self, f: F)
32    where
33        F: FnOnce(&mut W) -> &mut W,
34    {
35        let mut w = W::reset_value();
36        f(&mut w);
37        self.register.set(w.bits);
38    }
39    #[doc = r" Writes the reset value to the register"]
40    #[inline]
41    pub fn reset(&self) {
42        self.write(|w| w)
43    }
44}
45#[doc = r" Value of the field"]
46pub struct TENMSR {
47    bits: u32,
48}
49impl TENMSR {
50    #[doc = r" Value of the field as raw bits"]
51    #[inline]
52    pub fn bits(&self) -> u32 {
53        self.bits
54    }
55}
56#[doc = r" Value of the field"]
57pub struct SKEWR {
58    bits: bool,
59}
60impl SKEWR {
61    #[doc = r" Value of the field as raw bits"]
62    #[inline]
63    pub fn bit(&self) -> bool {
64        self.bits
65    }
66    #[doc = r" Returns `true` if the bit is clear (0)"]
67    #[inline]
68    pub fn bit_is_clear(&self) -> bool {
69        !self.bit()
70    }
71    #[doc = r" Returns `true` if the bit is set (1)"]
72    #[inline]
73    pub fn bit_is_set(&self) -> bool {
74        self.bit()
75    }
76}
77#[doc = r" Value of the field"]
78pub struct NOREFR {
79    bits: bool,
80}
81impl NOREFR {
82    #[doc = r" Value of the field as raw bits"]
83    #[inline]
84    pub fn bit(&self) -> bool {
85        self.bits
86    }
87    #[doc = r" Returns `true` if the bit is clear (0)"]
88    #[inline]
89    pub fn bit_is_clear(&self) -> bool {
90        !self.bit()
91    }
92    #[doc = r" Returns `true` if the bit is set (1)"]
93    #[inline]
94    pub fn bit_is_set(&self) -> bool {
95        self.bit()
96    }
97}
98#[doc = r" Proxy"]
99pub struct _TENMSW<'a> {
100    w: &'a mut W,
101}
102impl<'a> _TENMSW<'a> {
103    #[doc = r" Writes raw bits to the field"]
104    #[inline]
105    pub unsafe fn bits(self, value: u32) -> &'a mut W {
106        const MASK: u32 = 16777215;
107        const OFFSET: u8 = 0;
108        self.w.bits &= !((MASK as u32) << OFFSET);
109        self.w.bits |= ((value & MASK) as u32) << OFFSET;
110        self.w
111    }
112}
113#[doc = r" Proxy"]
114pub struct _SKEWW<'a> {
115    w: &'a mut W,
116}
117impl<'a> _SKEWW<'a> {
118    #[doc = r" Sets the field bit"]
119    pub fn set_bit(self) -> &'a mut W {
120        self.bit(true)
121    }
122    #[doc = r" Clears the field bit"]
123    pub fn clear_bit(self) -> &'a mut W {
124        self.bit(false)
125    }
126    #[doc = r" Writes raw bits to the field"]
127    #[inline]
128    pub fn bit(self, value: bool) -> &'a mut W {
129        const MASK: bool = true;
130        const OFFSET: u8 = 30;
131        self.w.bits &= !((MASK as u32) << OFFSET);
132        self.w.bits |= ((value & MASK) as u32) << OFFSET;
133        self.w
134    }
135}
136#[doc = r" Proxy"]
137pub struct _NOREFW<'a> {
138    w: &'a mut W,
139}
140impl<'a> _NOREFW<'a> {
141    #[doc = r" Sets the field bit"]
142    pub fn set_bit(self) -> &'a mut W {
143        self.bit(true)
144    }
145    #[doc = r" Clears the field bit"]
146    pub fn clear_bit(self) -> &'a mut W {
147        self.bit(false)
148    }
149    #[doc = r" Writes raw bits to the field"]
150    #[inline]
151    pub fn bit(self, value: bool) -> &'a mut W {
152        const MASK: bool = true;
153        const OFFSET: u8 = 31;
154        self.w.bits &= !((MASK as u32) << OFFSET);
155        self.w.bits |= ((value & MASK) as u32) << OFFSET;
156        self.w
157    }
158}
159impl R {
160    #[doc = r" Value of the register as raw bits"]
161    #[inline]
162    pub fn bits(&self) -> u32 {
163        self.bits
164    }
165    #[doc = "Bits 0:23 - Calibration value"]
166    #[inline]
167    pub fn tenms(&self) -> TENMSR {
168        let bits = {
169            const MASK: u32 = 16777215;
170            const OFFSET: u8 = 0;
171            ((self.bits >> OFFSET) & MASK as u32) as u32
172        };
173        TENMSR { bits }
174    }
175    #[doc = "Bit 30 - SKEW flag: Indicates whether the TENMS value is exact"]
176    #[inline]
177    pub fn skew(&self) -> SKEWR {
178        let bits = {
179            const MASK: bool = true;
180            const OFFSET: u8 = 30;
181            ((self.bits >> OFFSET) & MASK as u32) != 0
182        };
183        SKEWR { bits }
184    }
185    #[doc = "Bit 31 - NOREF flag. Reads as zero"]
186    #[inline]
187    pub fn noref(&self) -> NOREFR {
188        let bits = {
189            const MASK: bool = true;
190            const OFFSET: u8 = 31;
191            ((self.bits >> OFFSET) & MASK as u32) != 0
192        };
193        NOREFR { bits }
194    }
195}
196impl W {
197    #[doc = r" Reset value of the register"]
198    #[inline]
199    pub fn reset_value() -> W {
200        W { bits: 0 }
201    }
202    #[doc = r" Writes raw bits to the register"]
203    #[inline]
204    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
205        self.bits = bits;
206        self
207    }
208    #[doc = "Bits 0:23 - Calibration value"]
209    #[inline]
210    pub fn tenms(&mut self) -> _TENMSW {
211        _TENMSW { w: self }
212    }
213    #[doc = "Bit 30 - SKEW flag: Indicates whether the TENMS value is exact"]
214    #[inline]
215    pub fn skew(&mut self) -> _SKEWW {
216        _SKEWW { w: self }
217    }
218    #[doc = "Bit 31 - NOREF flag. Reads as zero"]
219    #[inline]
220    pub fn noref(&mut self) -> _NOREFW {
221        _NOREFW { w: self }
222    }
223}
stm32l4x2_pac/stk/calib.rs

stm32l4x2_pac/stk/
calib.rs
