stm32l4x2_pac/rng/
sr.rs

1#[doc = r" Value read from the register"]
2pub struct R {
3    bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7    bits: u32,
8}
9impl super::SR {
10    #[doc = r" Modifies the contents of the register"]
11    #[inline]
12    pub fn modify<F>(&self, f: F)
13    where
14        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15    {
16        let bits = self.register.get();
17        let r = R { bits: bits };
18        let mut w = W { bits: bits };
19        f(&r, &mut w);
20        self.register.set(w.bits);
21    }
22    #[doc = r" Reads the contents of the register"]
23    #[inline]
24    pub fn read(&self) -> R {
25        R {
26            bits: self.register.get(),
27        }
28    }
29    #[doc = r" Writes to the register"]
30    #[inline]
31    pub fn write<F>(&self, f: F)
32    where
33        F: FnOnce(&mut W) -> &mut W,
34    {
35        let mut w = W::reset_value();
36        f(&mut w);
37        self.register.set(w.bits);
38    }
39    #[doc = r" Writes the reset value to the register"]
40    #[inline]
41    pub fn reset(&self) {
42        self.write(|w| w)
43    }
44}
45#[doc = r" Value of the field"]
46pub struct SEISR {
47    bits: bool,
48}
49impl SEISR {
50    #[doc = r" Value of the field as raw bits"]
51    #[inline]
52    pub fn bit(&self) -> bool {
53        self.bits
54    }
55    #[doc = r" Returns `true` if the bit is clear (0)"]
56    #[inline]
57    pub fn bit_is_clear(&self) -> bool {
58        !self.bit()
59    }
60    #[doc = r" Returns `true` if the bit is set (1)"]
61    #[inline]
62    pub fn bit_is_set(&self) -> bool {
63        self.bit()
64    }
65}
66#[doc = r" Value of the field"]
67pub struct CEISR {
68    bits: bool,
69}
70impl CEISR {
71    #[doc = r" Value of the field as raw bits"]
72    #[inline]
73    pub fn bit(&self) -> bool {
74        self.bits
75    }
76    #[doc = r" Returns `true` if the bit is clear (0)"]
77    #[inline]
78    pub fn bit_is_clear(&self) -> bool {
79        !self.bit()
80    }
81    #[doc = r" Returns `true` if the bit is set (1)"]
82    #[inline]
83    pub fn bit_is_set(&self) -> bool {
84        self.bit()
85    }
86}
87#[doc = r" Value of the field"]
88pub struct SECSR {
89    bits: bool,
90}
91impl SECSR {
92    #[doc = r" Value of the field as raw bits"]
93    #[inline]
94    pub fn bit(&self) -> bool {
95        self.bits
96    }
97    #[doc = r" Returns `true` if the bit is clear (0)"]
98    #[inline]
99    pub fn bit_is_clear(&self) -> bool {
100        !self.bit()
101    }
102    #[doc = r" Returns `true` if the bit is set (1)"]
103    #[inline]
104    pub fn bit_is_set(&self) -> bool {
105        self.bit()
106    }
107}
108#[doc = r" Value of the field"]
109pub struct CECSR {
110    bits: bool,
111}
112impl CECSR {
113    #[doc = r" Value of the field as raw bits"]
114    #[inline]
115    pub fn bit(&self) -> bool {
116        self.bits
117    }
118    #[doc = r" Returns `true` if the bit is clear (0)"]
119    #[inline]
120    pub fn bit_is_clear(&self) -> bool {
121        !self.bit()
122    }
123    #[doc = r" Returns `true` if the bit is set (1)"]
124    #[inline]
125    pub fn bit_is_set(&self) -> bool {
126        self.bit()
127    }
128}
129#[doc = r" Value of the field"]
130pub struct DRDYR {
131    bits: bool,
132}
133impl DRDYR {
134    #[doc = r" Value of the field as raw bits"]
135    #[inline]
136    pub fn bit(&self) -> bool {
137        self.bits
138    }
139    #[doc = r" Returns `true` if the bit is clear (0)"]
140    #[inline]
141    pub fn bit_is_clear(&self) -> bool {
142        !self.bit()
143    }
144    #[doc = r" Returns `true` if the bit is set (1)"]
145    #[inline]
146    pub fn bit_is_set(&self) -> bool {
147        self.bit()
148    }
149}
150#[doc = r" Proxy"]
151pub struct _SEISW<'a> {
152    w: &'a mut W,
153}
154impl<'a> _SEISW<'a> {
155    #[doc = r" Sets the field bit"]
156    pub fn set_bit(self) -> &'a mut W {
157        self.bit(true)
158    }
159    #[doc = r" Clears the field bit"]
160    pub fn clear_bit(self) -> &'a mut W {
161        self.bit(false)
162    }
163    #[doc = r" Writes raw bits to the field"]
164    #[inline]
165    pub fn bit(self, value: bool) -> &'a mut W {
166        const MASK: bool = true;
167        const OFFSET: u8 = 6;
168        self.w.bits &= !((MASK as u32) << OFFSET);
169        self.w.bits |= ((value & MASK) as u32) << OFFSET;
170        self.w
171    }
172}
173#[doc = r" Proxy"]
174pub struct _CEISW<'a> {
175    w: &'a mut W,
176}
177impl<'a> _CEISW<'a> {
178    #[doc = r" Sets the field bit"]
179    pub fn set_bit(self) -> &'a mut W {
180        self.bit(true)
181    }
182    #[doc = r" Clears the field bit"]
183    pub fn clear_bit(self) -> &'a mut W {
184        self.bit(false)
185    }
186    #[doc = r" Writes raw bits to the field"]
187    #[inline]
188    pub fn bit(self, value: bool) -> &'a mut W {
189        const MASK: bool = true;
190        const OFFSET: u8 = 5;
191        self.w.bits &= !((MASK as u32) << OFFSET);
192        self.w.bits |= ((value & MASK) as u32) << OFFSET;
193        self.w
194    }
195}
196impl R {
197    #[doc = r" Value of the register as raw bits"]
198    #[inline]
199    pub fn bits(&self) -> u32 {
200        self.bits
201    }
202    #[doc = "Bit 6 - Seed error interrupt status"]
203    #[inline]
204    pub fn seis(&self) -> SEISR {
205        let bits = {
206            const MASK: bool = true;
207            const OFFSET: u8 = 6;
208            ((self.bits >> OFFSET) & MASK as u32) != 0
209        };
210        SEISR { bits }
211    }
212    #[doc = "Bit 5 - Clock error interrupt status"]
213    #[inline]
214    pub fn ceis(&self) -> CEISR {
215        let bits = {
216            const MASK: bool = true;
217            const OFFSET: u8 = 5;
218            ((self.bits >> OFFSET) & MASK as u32) != 0
219        };
220        CEISR { bits }
221    }
222    #[doc = "Bit 2 - Seed error current status"]
223    #[inline]
224    pub fn secs(&self) -> SECSR {
225        let bits = {
226            const MASK: bool = true;
227            const OFFSET: u8 = 2;
228            ((self.bits >> OFFSET) & MASK as u32) != 0
229        };
230        SECSR { bits }
231    }
232    #[doc = "Bit 1 - Clock error current status"]
233    #[inline]
234    pub fn cecs(&self) -> CECSR {
235        let bits = {
236            const MASK: bool = true;
237            const OFFSET: u8 = 1;
238            ((self.bits >> OFFSET) & MASK as u32) != 0
239        };
240        CECSR { bits }
241    }
242    #[doc = "Bit 0 - Data ready"]
243    #[inline]
244    pub fn drdy(&self) -> DRDYR {
245        let bits = {
246            const MASK: bool = true;
247            const OFFSET: u8 = 0;
248            ((self.bits >> OFFSET) & MASK as u32) != 0
249        };
250        DRDYR { bits }
251    }
252}
253impl W {
254    #[doc = r" Reset value of the register"]
255    #[inline]
256    pub fn reset_value() -> W {
257        W { bits: 0 }
258    }
259    #[doc = r" Writes raw bits to the register"]
260    #[inline]
261    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
262        self.bits = bits;
263        self
264    }
265    #[doc = "Bit 6 - Seed error interrupt status"]
266    #[inline]
267    pub fn seis(&mut self) -> _SEISW {
268        _SEISW { w: self }
269    }
270    #[doc = "Bit 5 - Clock error interrupt status"]
271    #[inline]
272    pub fn ceis(&mut self) -> _CEISW {
273        _CEISW { w: self }
274    }
275}
stm32l4x2_pac/rng/sr.rs

stm32l4x2_pac/rng/
sr.rs
