1#[doc = r" Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "0x00 - Clock control register"]
5 pub cr: CR,
6 #[doc = "0x04 - Internal clock sources calibration register"]
7 pub icscr: ICSCR,
8 #[doc = "0x08 - Clock configuration register"]
9 pub cfgr: CFGR,
10 #[doc = "0x0c - PLL configuration register"]
11 pub pllcfgr: PLLCFGR,
12 #[doc = "0x10 - PLLSAI1 configuration register"]
13 pub pllsai1cfgr: PLLSAI1CFGR,
14 _reserved0: [u8; 4usize],
15 #[doc = "0x18 - Clock interrupt enable register"]
16 pub cier: CIER,
17 #[doc = "0x1c - Clock interrupt flag register"]
18 pub cifr: CIFR,
19 #[doc = "0x20 - Clock interrupt clear register"]
20 pub cicr: CICR,
21 _reserved1: [u8; 4usize],
22 #[doc = "0x28 - AHB1 peripheral reset register"]
23 pub ahb1rstr: AHB1RSTR,
24 #[doc = "0x2c - AHB2 peripheral reset register"]
25 pub ahb2rstr: AHB2RSTR,
26 #[doc = "0x30 - AHB3 peripheral reset register"]
27 pub ahb3rstr: AHB3RSTR,
28 _reserved2: [u8; 4usize],
29 #[doc = "0x38 - APB1 peripheral reset register 1"]
30 pub apb1rstr1: APB1RSTR1,
31 #[doc = "0x3c - APB1 peripheral reset register 2"]
32 pub apb1rstr2: APB1RSTR2,
33 #[doc = "0x40 - APB2 peripheral reset register"]
34 pub apb2rstr: APB2RSTR,
35 _reserved3: [u8; 4usize],
36 #[doc = "0x48 - AHB1 peripheral clock enable register"]
37 pub ahb1enr: AHB1ENR,
38 #[doc = "0x4c - AHB2 peripheral clock enable register"]
39 pub ahb2enr: AHB2ENR,
40 #[doc = "0x50 - AHB3 peripheral clock enable register"]
41 pub ahb3enr: AHB3ENR,
42 _reserved4: [u8; 4usize],
43 #[doc = "0x58 - APB1ENR1"]
44 pub apb1enr1: APB1ENR1,
45 #[doc = "0x5c - APB1 peripheral clock enable register 2"]
46 pub apb1enr2: APB1ENR2,
47 #[doc = "0x60 - APB2ENR"]
48 pub apb2enr: APB2ENR,
49 _reserved5: [u8; 4usize],
50 #[doc = "0x68 - AHB1 peripheral clocks enable in Sleep and Stop modes register"]
51 pub ahb1smenr: AHB1SMENR,
52 #[doc = "0x6c - AHB2 peripheral clocks enable in Sleep and Stop modes register"]
53 pub ahb2smenr: AHB2SMENR,
54 #[doc = "0x70 - AHB3 peripheral clocks enable in Sleep and Stop modes register"]
55 pub ahb3smenr: AHB3SMENR,
56 _reserved6: [u8; 4usize],
57 #[doc = "0x78 - APB1SMENR1"]
58 pub apb1smenr1: APB1SMENR1,
59 #[doc = "0x7c - APB1 peripheral clocks enable in Sleep and Stop modes register 2"]
60 pub apb1smenr2: APB1SMENR2,
61 #[doc = "0x80 - APB2SMENR"]
62 pub apb2smenr: APB2SMENR,
63 _reserved7: [u8; 4usize],
64 #[doc = "0x88 - CCIPR"]
65 pub ccipr: CCIPR,
66 _reserved8: [u8; 4usize],
67 #[doc = "0x90 - BDCR"]
68 pub bdcr: BDCR,
69 #[doc = "0x94 - CSR"]
70 pub csr: CSR,
71 #[doc = "0x98 - Clock recovery RC register"]
72 pub crrcr: CRRCR,
73}
74#[doc = "Clock control register"]
75pub struct CR {
76 register: ::vcell::VolatileCell<u32>,
77}
78#[doc = "Clock control register"]
79pub mod cr;
80#[doc = "Internal clock sources calibration register"]
81pub struct ICSCR {
82 register: ::vcell::VolatileCell<u32>,
83}
84#[doc = "Internal clock sources calibration register"]
85pub mod icscr;
86#[doc = "Clock configuration register"]
87pub struct CFGR {
88 register: ::vcell::VolatileCell<u32>,
89}
90#[doc = "Clock configuration register"]
91pub mod cfgr;
92#[doc = "PLL configuration register"]
93pub struct PLLCFGR {
94 register: ::vcell::VolatileCell<u32>,
95}
96#[doc = "PLL configuration register"]
97pub mod pllcfgr;
98#[doc = "PLLSAI1 configuration register"]
99pub struct PLLSAI1CFGR {
100 register: ::vcell::VolatileCell<u32>,
101}
102#[doc = "PLLSAI1 configuration register"]
103pub mod pllsai1cfgr;
104#[doc = "Clock interrupt enable register"]
105pub struct CIER {
106 register: ::vcell::VolatileCell<u32>,
107}
108#[doc = "Clock interrupt enable register"]
109pub mod cier;
110#[doc = "Clock interrupt flag register"]
111pub struct CIFR {
112 register: ::vcell::VolatileCell<u32>,
113}
114#[doc = "Clock interrupt flag register"]
115pub mod cifr;
116#[doc = "Clock interrupt clear register"]
117pub struct CICR {
118 register: ::vcell::VolatileCell<u32>,
119}
120#[doc = "Clock interrupt clear register"]
121pub mod cicr;
122#[doc = "AHB1 peripheral reset register"]
123pub struct AHB1RSTR {
124 register: ::vcell::VolatileCell<u32>,
125}
126#[doc = "AHB1 peripheral reset register"]
127pub mod ahb1rstr;
128#[doc = "AHB2 peripheral reset register"]
129pub struct AHB2RSTR {
130 register: ::vcell::VolatileCell<u32>,
131}
132#[doc = "AHB2 peripheral reset register"]
133pub mod ahb2rstr;
134#[doc = "AHB3 peripheral reset register"]
135pub struct AHB3RSTR {
136 register: ::vcell::VolatileCell<u32>,
137}
138#[doc = "AHB3 peripheral reset register"]
139pub mod ahb3rstr;
140#[doc = "APB1 peripheral reset register 1"]
141pub struct APB1RSTR1 {
142 register: ::vcell::VolatileCell<u32>,
143}
144#[doc = "APB1 peripheral reset register 1"]
145pub mod apb1rstr1;
146#[doc = "APB1 peripheral reset register 2"]
147pub struct APB1RSTR2 {
148 register: ::vcell::VolatileCell<u32>,
149}
150#[doc = "APB1 peripheral reset register 2"]
151pub mod apb1rstr2;
152#[doc = "APB2 peripheral reset register"]
153pub struct APB2RSTR {
154 register: ::vcell::VolatileCell<u32>,
155}
156#[doc = "APB2 peripheral reset register"]
157pub mod apb2rstr;
158#[doc = "AHB1 peripheral clock enable register"]
159pub struct AHB1ENR {
160 register: ::vcell::VolatileCell<u32>,
161}
162#[doc = "AHB1 peripheral clock enable register"]
163pub mod ahb1enr;
164#[doc = "AHB2 peripheral clock enable register"]
165pub struct AHB2ENR {
166 register: ::vcell::VolatileCell<u32>,
167}
168#[doc = "AHB2 peripheral clock enable register"]
169pub mod ahb2enr;
170#[doc = "AHB3 peripheral clock enable register"]
171pub struct AHB3ENR {
172 register: ::vcell::VolatileCell<u32>,
173}
174#[doc = "AHB3 peripheral clock enable register"]
175pub mod ahb3enr;
176#[doc = "APB1ENR1"]
177pub struct APB1ENR1 {
178 register: ::vcell::VolatileCell<u32>,
179}
180#[doc = "APB1ENR1"]
181pub mod apb1enr1;
182#[doc = "APB1 peripheral clock enable register 2"]
183pub struct APB1ENR2 {
184 register: ::vcell::VolatileCell<u32>,
185}
186#[doc = "APB1 peripheral clock enable register 2"]
187pub mod apb1enr2;
188#[doc = "APB2ENR"]
189pub struct APB2ENR {
190 register: ::vcell::VolatileCell<u32>,
191}
192#[doc = "APB2ENR"]
193pub mod apb2enr;
194#[doc = "AHB1 peripheral clocks enable in Sleep and Stop modes register"]
195pub struct AHB1SMENR {
196 register: ::vcell::VolatileCell<u32>,
197}
198#[doc = "AHB1 peripheral clocks enable in Sleep and Stop modes register"]
199pub mod ahb1smenr;
200#[doc = "AHB2 peripheral clocks enable in Sleep and Stop modes register"]
201pub struct AHB2SMENR {
202 register: ::vcell::VolatileCell<u32>,
203}
204#[doc = "AHB2 peripheral clocks enable in Sleep and Stop modes register"]
205pub mod ahb2smenr;
206#[doc = "AHB3 peripheral clocks enable in Sleep and Stop modes register"]
207pub struct AHB3SMENR {
208 register: ::vcell::VolatileCell<u32>,
209}
210#[doc = "AHB3 peripheral clocks enable in Sleep and Stop modes register"]
211pub mod ahb3smenr;
212#[doc = "APB1SMENR1"]
213pub struct APB1SMENR1 {
214 register: ::vcell::VolatileCell<u32>,
215}
216#[doc = "APB1SMENR1"]
217pub mod apb1smenr1;
218#[doc = "APB1 peripheral clocks enable in Sleep and Stop modes register 2"]
219pub struct APB1SMENR2 {
220 register: ::vcell::VolatileCell<u32>,
221}
222#[doc = "APB1 peripheral clocks enable in Sleep and Stop modes register 2"]
223pub mod apb1smenr2;
224#[doc = "APB2SMENR"]
225pub struct APB2SMENR {
226 register: ::vcell::VolatileCell<u32>,
227}
228#[doc = "APB2SMENR"]
229pub mod apb2smenr;
230#[doc = "CCIPR"]
231pub struct CCIPR {
232 register: ::vcell::VolatileCell<u32>,
233}
234#[doc = "CCIPR"]
235pub mod ccipr;
236#[doc = "BDCR"]
237pub struct BDCR {
238 register: ::vcell::VolatileCell<u32>,
239}
240#[doc = "BDCR"]
241pub mod bdcr;
242#[doc = "CSR"]
243pub struct CSR {
244 register: ::vcell::VolatileCell<u32>,
245}
246#[doc = "CSR"]
247pub mod csr;
248#[doc = "Clock recovery RC register"]
249pub struct CRRCR {
250 register: ::vcell::VolatileCell<u32>,
251}
252#[doc = "Clock recovery RC register"]
253pub mod crrcr;