stm32l4x2_pac/lptim1/
isr.rs

1#[doc = r" Value read from the register"]
2pub struct R {
3    bits: u32,
4}
5impl super::ISR {
6    #[doc = r" Reads the contents of the register"]
7    #[inline]
8    pub fn read(&self) -> R {
9        R {
10            bits: self.register.get(),
11        }
12    }
13}
14#[doc = r" Value of the field"]
15pub struct DOWNR {
16    bits: bool,
17}
18impl DOWNR {
19    #[doc = r" Value of the field as raw bits"]
20    #[inline]
21    pub fn bit(&self) -> bool {
22        self.bits
23    }
24    #[doc = r" Returns `true` if the bit is clear (0)"]
25    #[inline]
26    pub fn bit_is_clear(&self) -> bool {
27        !self.bit()
28    }
29    #[doc = r" Returns `true` if the bit is set (1)"]
30    #[inline]
31    pub fn bit_is_set(&self) -> bool {
32        self.bit()
33    }
34}
35#[doc = r" Value of the field"]
36pub struct UPR {
37    bits: bool,
38}
39impl UPR {
40    #[doc = r" Value of the field as raw bits"]
41    #[inline]
42    pub fn bit(&self) -> bool {
43        self.bits
44    }
45    #[doc = r" Returns `true` if the bit is clear (0)"]
46    #[inline]
47    pub fn bit_is_clear(&self) -> bool {
48        !self.bit()
49    }
50    #[doc = r" Returns `true` if the bit is set (1)"]
51    #[inline]
52    pub fn bit_is_set(&self) -> bool {
53        self.bit()
54    }
55}
56#[doc = r" Value of the field"]
57pub struct ARROKR {
58    bits: bool,
59}
60impl ARROKR {
61    #[doc = r" Value of the field as raw bits"]
62    #[inline]
63    pub fn bit(&self) -> bool {
64        self.bits
65    }
66    #[doc = r" Returns `true` if the bit is clear (0)"]
67    #[inline]
68    pub fn bit_is_clear(&self) -> bool {
69        !self.bit()
70    }
71    #[doc = r" Returns `true` if the bit is set (1)"]
72    #[inline]
73    pub fn bit_is_set(&self) -> bool {
74        self.bit()
75    }
76}
77#[doc = r" Value of the field"]
78pub struct CMPOKR {
79    bits: bool,
80}
81impl CMPOKR {
82    #[doc = r" Value of the field as raw bits"]
83    #[inline]
84    pub fn bit(&self) -> bool {
85        self.bits
86    }
87    #[doc = r" Returns `true` if the bit is clear (0)"]
88    #[inline]
89    pub fn bit_is_clear(&self) -> bool {
90        !self.bit()
91    }
92    #[doc = r" Returns `true` if the bit is set (1)"]
93    #[inline]
94    pub fn bit_is_set(&self) -> bool {
95        self.bit()
96    }
97}
98#[doc = r" Value of the field"]
99pub struct EXTTRIGR {
100    bits: bool,
101}
102impl EXTTRIGR {
103    #[doc = r" Value of the field as raw bits"]
104    #[inline]
105    pub fn bit(&self) -> bool {
106        self.bits
107    }
108    #[doc = r" Returns `true` if the bit is clear (0)"]
109    #[inline]
110    pub fn bit_is_clear(&self) -> bool {
111        !self.bit()
112    }
113    #[doc = r" Returns `true` if the bit is set (1)"]
114    #[inline]
115    pub fn bit_is_set(&self) -> bool {
116        self.bit()
117    }
118}
119#[doc = r" Value of the field"]
120pub struct ARRMR {
121    bits: bool,
122}
123impl ARRMR {
124    #[doc = r" Value of the field as raw bits"]
125    #[inline]
126    pub fn bit(&self) -> bool {
127        self.bits
128    }
129    #[doc = r" Returns `true` if the bit is clear (0)"]
130    #[inline]
131    pub fn bit_is_clear(&self) -> bool {
132        !self.bit()
133    }
134    #[doc = r" Returns `true` if the bit is set (1)"]
135    #[inline]
136    pub fn bit_is_set(&self) -> bool {
137        self.bit()
138    }
139}
140#[doc = r" Value of the field"]
141pub struct CMPMR {
142    bits: bool,
143}
144impl CMPMR {
145    #[doc = r" Value of the field as raw bits"]
146    #[inline]
147    pub fn bit(&self) -> bool {
148        self.bits
149    }
150    #[doc = r" Returns `true` if the bit is clear (0)"]
151    #[inline]
152    pub fn bit_is_clear(&self) -> bool {
153        !self.bit()
154    }
155    #[doc = r" Returns `true` if the bit is set (1)"]
156    #[inline]
157    pub fn bit_is_set(&self) -> bool {
158        self.bit()
159    }
160}
161impl R {
162    #[doc = r" Value of the register as raw bits"]
163    #[inline]
164    pub fn bits(&self) -> u32 {
165        self.bits
166    }
167    #[doc = "Bit 6 - Counter direction change up to down"]
168    #[inline]
169    pub fn down(&self) -> DOWNR {
170        let bits = {
171            const MASK: bool = true;
172            const OFFSET: u8 = 6;
173            ((self.bits >> OFFSET) & MASK as u32) != 0
174        };
175        DOWNR { bits }
176    }
177    #[doc = "Bit 5 - Counter direction change down to up"]
178    #[inline]
179    pub fn up(&self) -> UPR {
180        let bits = {
181            const MASK: bool = true;
182            const OFFSET: u8 = 5;
183            ((self.bits >> OFFSET) & MASK as u32) != 0
184        };
185        UPR { bits }
186    }
187    #[doc = "Bit 4 - Autoreload register update OK"]
188    #[inline]
189    pub fn arrok(&self) -> ARROKR {
190        let bits = {
191            const MASK: bool = true;
192            const OFFSET: u8 = 4;
193            ((self.bits >> OFFSET) & MASK as u32) != 0
194        };
195        ARROKR { bits }
196    }
197    #[doc = "Bit 3 - Compare register update OK"]
198    #[inline]
199    pub fn cmpok(&self) -> CMPOKR {
200        let bits = {
201            const MASK: bool = true;
202            const OFFSET: u8 = 3;
203            ((self.bits >> OFFSET) & MASK as u32) != 0
204        };
205        CMPOKR { bits }
206    }
207    #[doc = "Bit 2 - External trigger edge event"]
208    #[inline]
209    pub fn exttrig(&self) -> EXTTRIGR {
210        let bits = {
211            const MASK: bool = true;
212            const OFFSET: u8 = 2;
213            ((self.bits >> OFFSET) & MASK as u32) != 0
214        };
215        EXTTRIGR { bits }
216    }
217    #[doc = "Bit 1 - Autoreload match"]
218    #[inline]
219    pub fn arrm(&self) -> ARRMR {
220        let bits = {
221            const MASK: bool = true;
222            const OFFSET: u8 = 1;
223            ((self.bits >> OFFSET) & MASK as u32) != 0
224        };
225        ARRMR { bits }
226    }
227    #[doc = "Bit 0 - Compare match"]
228    #[inline]
229    pub fn cmpm(&self) -> CMPMR {
230        let bits = {
231            const MASK: bool = true;
232            const OFFSET: u8 = 0;
233            ((self.bits >> OFFSET) & MASK as u32) != 0
234        };
235        CMPMR { bits }
236    }
237}
stm32l4x2_pac/lptim1/isr.rs

stm32l4x2_pac/lptim1/
isr.rs
