1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::CR {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = r" Value of the field"]
46pub struct BIASR {
47 bits: u8,
48}
49impl BIASR {
50 #[doc = r" Value of the field as raw bits"]
51 #[inline]
52 pub fn bits(&self) -> u8 {
53 self.bits
54 }
55}
56#[doc = r" Value of the field"]
57pub struct DUTYR {
58 bits: u8,
59}
60impl DUTYR {
61 #[doc = r" Value of the field as raw bits"]
62 #[inline]
63 pub fn bits(&self) -> u8 {
64 self.bits
65 }
66}
67#[doc = r" Value of the field"]
68pub struct VSELR {
69 bits: bool,
70}
71impl VSELR {
72 #[doc = r" Value of the field as raw bits"]
73 #[inline]
74 pub fn bit(&self) -> bool {
75 self.bits
76 }
77 #[doc = r" Returns `true` if the bit is clear (0)"]
78 #[inline]
79 pub fn bit_is_clear(&self) -> bool {
80 !self.bit()
81 }
82 #[doc = r" Returns `true` if the bit is set (1)"]
83 #[inline]
84 pub fn bit_is_set(&self) -> bool {
85 self.bit()
86 }
87}
88#[doc = r" Value of the field"]
89pub struct LCDENR {
90 bits: bool,
91}
92impl LCDENR {
93 #[doc = r" Value of the field as raw bits"]
94 #[inline]
95 pub fn bit(&self) -> bool {
96 self.bits
97 }
98 #[doc = r" Returns `true` if the bit is clear (0)"]
99 #[inline]
100 pub fn bit_is_clear(&self) -> bool {
101 !self.bit()
102 }
103 #[doc = r" Returns `true` if the bit is set (1)"]
104 #[inline]
105 pub fn bit_is_set(&self) -> bool {
106 self.bit()
107 }
108}
109#[doc = r" Value of the field"]
110pub struct MUX_SEGR {
111 bits: bool,
112}
113impl MUX_SEGR {
114 #[doc = r" Value of the field as raw bits"]
115 #[inline]
116 pub fn bit(&self) -> bool {
117 self.bits
118 }
119 #[doc = r" Returns `true` if the bit is clear (0)"]
120 #[inline]
121 pub fn bit_is_clear(&self) -> bool {
122 !self.bit()
123 }
124 #[doc = r" Returns `true` if the bit is set (1)"]
125 #[inline]
126 pub fn bit_is_set(&self) -> bool {
127 self.bit()
128 }
129}
130#[doc = r" Value of the field"]
131pub struct BUFENR {
132 bits: bool,
133}
134impl BUFENR {
135 #[doc = r" Value of the field as raw bits"]
136 #[inline]
137 pub fn bit(&self) -> bool {
138 self.bits
139 }
140 #[doc = r" Returns `true` if the bit is clear (0)"]
141 #[inline]
142 pub fn bit_is_clear(&self) -> bool {
143 !self.bit()
144 }
145 #[doc = r" Returns `true` if the bit is set (1)"]
146 #[inline]
147 pub fn bit_is_set(&self) -> bool {
148 self.bit()
149 }
150}
151#[doc = r" Proxy"]
152pub struct _BIASW<'a> {
153 w: &'a mut W,
154}
155impl<'a> _BIASW<'a> {
156 #[doc = r" Writes raw bits to the field"]
157 #[inline]
158 pub unsafe fn bits(self, value: u8) -> &'a mut W {
159 const MASK: u8 = 3;
160 const OFFSET: u8 = 5;
161 self.w.bits &= !((MASK as u32) << OFFSET);
162 self.w.bits |= ((value & MASK) as u32) << OFFSET;
163 self.w
164 }
165}
166#[doc = r" Proxy"]
167pub struct _DUTYW<'a> {
168 w: &'a mut W,
169}
170impl<'a> _DUTYW<'a> {
171 #[doc = r" Writes raw bits to the field"]
172 #[inline]
173 pub unsafe fn bits(self, value: u8) -> &'a mut W {
174 const MASK: u8 = 7;
175 const OFFSET: u8 = 2;
176 self.w.bits &= !((MASK as u32) << OFFSET);
177 self.w.bits |= ((value & MASK) as u32) << OFFSET;
178 self.w
179 }
180}
181#[doc = r" Proxy"]
182pub struct _VSELW<'a> {
183 w: &'a mut W,
184}
185impl<'a> _VSELW<'a> {
186 #[doc = r" Sets the field bit"]
187 pub fn set_bit(self) -> &'a mut W {
188 self.bit(true)
189 }
190 #[doc = r" Clears the field bit"]
191 pub fn clear_bit(self) -> &'a mut W {
192 self.bit(false)
193 }
194 #[doc = r" Writes raw bits to the field"]
195 #[inline]
196 pub fn bit(self, value: bool) -> &'a mut W {
197 const MASK: bool = true;
198 const OFFSET: u8 = 1;
199 self.w.bits &= !((MASK as u32) << OFFSET);
200 self.w.bits |= ((value & MASK) as u32) << OFFSET;
201 self.w
202 }
203}
204#[doc = r" Proxy"]
205pub struct _LCDENW<'a> {
206 w: &'a mut W,
207}
208impl<'a> _LCDENW<'a> {
209 #[doc = r" Sets the field bit"]
210 pub fn set_bit(self) -> &'a mut W {
211 self.bit(true)
212 }
213 #[doc = r" Clears the field bit"]
214 pub fn clear_bit(self) -> &'a mut W {
215 self.bit(false)
216 }
217 #[doc = r" Writes raw bits to the field"]
218 #[inline]
219 pub fn bit(self, value: bool) -> &'a mut W {
220 const MASK: bool = true;
221 const OFFSET: u8 = 0;
222 self.w.bits &= !((MASK as u32) << OFFSET);
223 self.w.bits |= ((value & MASK) as u32) << OFFSET;
224 self.w
225 }
226}
227#[doc = r" Proxy"]
228pub struct _MUX_SEGW<'a> {
229 w: &'a mut W,
230}
231impl<'a> _MUX_SEGW<'a> {
232 #[doc = r" Sets the field bit"]
233 pub fn set_bit(self) -> &'a mut W {
234 self.bit(true)
235 }
236 #[doc = r" Clears the field bit"]
237 pub fn clear_bit(self) -> &'a mut W {
238 self.bit(false)
239 }
240 #[doc = r" Writes raw bits to the field"]
241 #[inline]
242 pub fn bit(self, value: bool) -> &'a mut W {
243 const MASK: bool = true;
244 const OFFSET: u8 = 7;
245 self.w.bits &= !((MASK as u32) << OFFSET);
246 self.w.bits |= ((value & MASK) as u32) << OFFSET;
247 self.w
248 }
249}
250#[doc = r" Proxy"]
251pub struct _BUFENW<'a> {
252 w: &'a mut W,
253}
254impl<'a> _BUFENW<'a> {
255 #[doc = r" Sets the field bit"]
256 pub fn set_bit(self) -> &'a mut W {
257 self.bit(true)
258 }
259 #[doc = r" Clears the field bit"]
260 pub fn clear_bit(self) -> &'a mut W {
261 self.bit(false)
262 }
263 #[doc = r" Writes raw bits to the field"]
264 #[inline]
265 pub fn bit(self, value: bool) -> &'a mut W {
266 const MASK: bool = true;
267 const OFFSET: u8 = 8;
268 self.w.bits &= !((MASK as u32) << OFFSET);
269 self.w.bits |= ((value & MASK) as u32) << OFFSET;
270 self.w
271 }
272}
273impl R {
274 #[doc = r" Value of the register as raw bits"]
275 #[inline]
276 pub fn bits(&self) -> u32 {
277 self.bits
278 }
279 #[doc = "Bits 5:6 - Bias selector"]
280 #[inline]
281 pub fn bias(&self) -> BIASR {
282 let bits = {
283 const MASK: u8 = 3;
284 const OFFSET: u8 = 5;
285 ((self.bits >> OFFSET) & MASK as u32) as u8
286 };
287 BIASR { bits }
288 }
289 #[doc = "Bits 2:4 - Duty selection"]
290 #[inline]
291 pub fn duty(&self) -> DUTYR {
292 let bits = {
293 const MASK: u8 = 7;
294 const OFFSET: u8 = 2;
295 ((self.bits >> OFFSET) & MASK as u32) as u8
296 };
297 DUTYR { bits }
298 }
299 #[doc = "Bit 1 - Voltage source selection"]
300 #[inline]
301 pub fn vsel(&self) -> VSELR {
302 let bits = {
303 const MASK: bool = true;
304 const OFFSET: u8 = 1;
305 ((self.bits >> OFFSET) & MASK as u32) != 0
306 };
307 VSELR { bits }
308 }
309 #[doc = "Bit 0 - LCD controller enable"]
310 #[inline]
311 pub fn lcden(&self) -> LCDENR {
312 let bits = {
313 const MASK: bool = true;
314 const OFFSET: u8 = 0;
315 ((self.bits >> OFFSET) & MASK as u32) != 0
316 };
317 LCDENR { bits }
318 }
319 #[doc = "Bit 7 - Mux segment enable"]
320 #[inline]
321 pub fn mux_seg(&self) -> MUX_SEGR {
322 let bits = {
323 const MASK: bool = true;
324 const OFFSET: u8 = 7;
325 ((self.bits >> OFFSET) & MASK as u32) != 0
326 };
327 MUX_SEGR { bits }
328 }
329 #[doc = "Bit 8 - Voltage output buffer enable"]
330 #[inline]
331 pub fn bufen(&self) -> BUFENR {
332 let bits = {
333 const MASK: bool = true;
334 const OFFSET: u8 = 8;
335 ((self.bits >> OFFSET) & MASK as u32) != 0
336 };
337 BUFENR { bits }
338 }
339}
340impl W {
341 #[doc = r" Reset value of the register"]
342 #[inline]
343 pub fn reset_value() -> W {
344 W { bits: 0 }
345 }
346 #[doc = r" Writes raw bits to the register"]
347 #[inline]
348 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
349 self.bits = bits;
350 self
351 }
352 #[doc = "Bits 5:6 - Bias selector"]
353 #[inline]
354 pub fn bias(&mut self) -> _BIASW {
355 _BIASW { w: self }
356 }
357 #[doc = "Bits 2:4 - Duty selection"]
358 #[inline]
359 pub fn duty(&mut self) -> _DUTYW {
360 _DUTYW { w: self }
361 }
362 #[doc = "Bit 1 - Voltage source selection"]
363 #[inline]
364 pub fn vsel(&mut self) -> _VSELW {
365 _VSELW { w: self }
366 }
367 #[doc = "Bit 0 - LCD controller enable"]
368 #[inline]
369 pub fn lcden(&mut self) -> _LCDENW {
370 _LCDENW { w: self }
371 }
372 #[doc = "Bit 7 - Mux segment enable"]
373 #[inline]
374 pub fn mux_seg(&mut self) -> _MUX_SEGW {
375 _MUX_SEGW { w: self }
376 }
377 #[doc = "Bit 8 - Voltage output buffer enable"]
378 #[inline]
379 pub fn bufen(&mut self) -> _BUFENW {
380 _BUFENW { w: self }
381 }
382}