stm32l4x2_pac/flash/
acr.rs

1#[doc = r" Value read from the register"]
2pub struct R {
3    bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7    bits: u32,
8}
9impl super::ACR {
10    #[doc = r" Modifies the contents of the register"]
11    #[inline]
12    pub fn modify<F>(&self, f: F)
13    where
14        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15    {
16        let bits = self.register.get();
17        let r = R { bits: bits };
18        let mut w = W { bits: bits };
19        f(&r, &mut w);
20        self.register.set(w.bits);
21    }
22    #[doc = r" Reads the contents of the register"]
23    #[inline]
24    pub fn read(&self) -> R {
25        R {
26            bits: self.register.get(),
27        }
28    }
29    #[doc = r" Writes to the register"]
30    #[inline]
31    pub fn write<F>(&self, f: F)
32    where
33        F: FnOnce(&mut W) -> &mut W,
34    {
35        let mut w = W::reset_value();
36        f(&mut w);
37        self.register.set(w.bits);
38    }
39    #[doc = r" Writes the reset value to the register"]
40    #[inline]
41    pub fn reset(&self) {
42        self.write(|w| w)
43    }
44}
45#[doc = r" Value of the field"]
46pub struct LATENCYR {
47    bits: u8,
48}
49impl LATENCYR {
50    #[doc = r" Value of the field as raw bits"]
51    #[inline]
52    pub fn bits(&self) -> u8 {
53        self.bits
54    }
55}
56#[doc = r" Value of the field"]
57pub struct PRFTENR {
58    bits: bool,
59}
60impl PRFTENR {
61    #[doc = r" Value of the field as raw bits"]
62    #[inline]
63    pub fn bit(&self) -> bool {
64        self.bits
65    }
66    #[doc = r" Returns `true` if the bit is clear (0)"]
67    #[inline]
68    pub fn bit_is_clear(&self) -> bool {
69        !self.bit()
70    }
71    #[doc = r" Returns `true` if the bit is set (1)"]
72    #[inline]
73    pub fn bit_is_set(&self) -> bool {
74        self.bit()
75    }
76}
77#[doc = r" Value of the field"]
78pub struct ICENR {
79    bits: bool,
80}
81impl ICENR {
82    #[doc = r" Value of the field as raw bits"]
83    #[inline]
84    pub fn bit(&self) -> bool {
85        self.bits
86    }
87    #[doc = r" Returns `true` if the bit is clear (0)"]
88    #[inline]
89    pub fn bit_is_clear(&self) -> bool {
90        !self.bit()
91    }
92    #[doc = r" Returns `true` if the bit is set (1)"]
93    #[inline]
94    pub fn bit_is_set(&self) -> bool {
95        self.bit()
96    }
97}
98#[doc = r" Value of the field"]
99pub struct DCENR {
100    bits: bool,
101}
102impl DCENR {
103    #[doc = r" Value of the field as raw bits"]
104    #[inline]
105    pub fn bit(&self) -> bool {
106        self.bits
107    }
108    #[doc = r" Returns `true` if the bit is clear (0)"]
109    #[inline]
110    pub fn bit_is_clear(&self) -> bool {
111        !self.bit()
112    }
113    #[doc = r" Returns `true` if the bit is set (1)"]
114    #[inline]
115    pub fn bit_is_set(&self) -> bool {
116        self.bit()
117    }
118}
119#[doc = r" Value of the field"]
120pub struct ICRSTR {
121    bits: bool,
122}
123impl ICRSTR {
124    #[doc = r" Value of the field as raw bits"]
125    #[inline]
126    pub fn bit(&self) -> bool {
127        self.bits
128    }
129    #[doc = r" Returns `true` if the bit is clear (0)"]
130    #[inline]
131    pub fn bit_is_clear(&self) -> bool {
132        !self.bit()
133    }
134    #[doc = r" Returns `true` if the bit is set (1)"]
135    #[inline]
136    pub fn bit_is_set(&self) -> bool {
137        self.bit()
138    }
139}
140#[doc = r" Value of the field"]
141pub struct DCRSTR {
142    bits: bool,
143}
144impl DCRSTR {
145    #[doc = r" Value of the field as raw bits"]
146    #[inline]
147    pub fn bit(&self) -> bool {
148        self.bits
149    }
150    #[doc = r" Returns `true` if the bit is clear (0)"]
151    #[inline]
152    pub fn bit_is_clear(&self) -> bool {
153        !self.bit()
154    }
155    #[doc = r" Returns `true` if the bit is set (1)"]
156    #[inline]
157    pub fn bit_is_set(&self) -> bool {
158        self.bit()
159    }
160}
161#[doc = r" Value of the field"]
162pub struct RUN_PDR {
163    bits: bool,
164}
165impl RUN_PDR {
166    #[doc = r" Value of the field as raw bits"]
167    #[inline]
168    pub fn bit(&self) -> bool {
169        self.bits
170    }
171    #[doc = r" Returns `true` if the bit is clear (0)"]
172    #[inline]
173    pub fn bit_is_clear(&self) -> bool {
174        !self.bit()
175    }
176    #[doc = r" Returns `true` if the bit is set (1)"]
177    #[inline]
178    pub fn bit_is_set(&self) -> bool {
179        self.bit()
180    }
181}
182#[doc = r" Value of the field"]
183pub struct SLEEP_PDR {
184    bits: bool,
185}
186impl SLEEP_PDR {
187    #[doc = r" Value of the field as raw bits"]
188    #[inline]
189    pub fn bit(&self) -> bool {
190        self.bits
191    }
192    #[doc = r" Returns `true` if the bit is clear (0)"]
193    #[inline]
194    pub fn bit_is_clear(&self) -> bool {
195        !self.bit()
196    }
197    #[doc = r" Returns `true` if the bit is set (1)"]
198    #[inline]
199    pub fn bit_is_set(&self) -> bool {
200        self.bit()
201    }
202}
203#[doc = r" Proxy"]
204pub struct _LATENCYW<'a> {
205    w: &'a mut W,
206}
207impl<'a> _LATENCYW<'a> {
208    #[doc = r" Writes raw bits to the field"]
209    #[inline]
210    pub unsafe fn bits(self, value: u8) -> &'a mut W {
211        const MASK: u8 = 7;
212        const OFFSET: u8 = 0;
213        self.w.bits &= !((MASK as u32) << OFFSET);
214        self.w.bits |= ((value & MASK) as u32) << OFFSET;
215        self.w
216    }
217}
218#[doc = r" Proxy"]
219pub struct _PRFTENW<'a> {
220    w: &'a mut W,
221}
222impl<'a> _PRFTENW<'a> {
223    #[doc = r" Sets the field bit"]
224    pub fn set_bit(self) -> &'a mut W {
225        self.bit(true)
226    }
227    #[doc = r" Clears the field bit"]
228    pub fn clear_bit(self) -> &'a mut W {
229        self.bit(false)
230    }
231    #[doc = r" Writes raw bits to the field"]
232    #[inline]
233    pub fn bit(self, value: bool) -> &'a mut W {
234        const MASK: bool = true;
235        const OFFSET: u8 = 8;
236        self.w.bits &= !((MASK as u32) << OFFSET);
237        self.w.bits |= ((value & MASK) as u32) << OFFSET;
238        self.w
239    }
240}
241#[doc = r" Proxy"]
242pub struct _ICENW<'a> {
243    w: &'a mut W,
244}
245impl<'a> _ICENW<'a> {
246    #[doc = r" Sets the field bit"]
247    pub fn set_bit(self) -> &'a mut W {
248        self.bit(true)
249    }
250    #[doc = r" Clears the field bit"]
251    pub fn clear_bit(self) -> &'a mut W {
252        self.bit(false)
253    }
254    #[doc = r" Writes raw bits to the field"]
255    #[inline]
256    pub fn bit(self, value: bool) -> &'a mut W {
257        const MASK: bool = true;
258        const OFFSET: u8 = 9;
259        self.w.bits &= !((MASK as u32) << OFFSET);
260        self.w.bits |= ((value & MASK) as u32) << OFFSET;
261        self.w
262    }
263}
264#[doc = r" Proxy"]
265pub struct _DCENW<'a> {
266    w: &'a mut W,
267}
268impl<'a> _DCENW<'a> {
269    #[doc = r" Sets the field bit"]
270    pub fn set_bit(self) -> &'a mut W {
271        self.bit(true)
272    }
273    #[doc = r" Clears the field bit"]
274    pub fn clear_bit(self) -> &'a mut W {
275        self.bit(false)
276    }
277    #[doc = r" Writes raw bits to the field"]
278    #[inline]
279    pub fn bit(self, value: bool) -> &'a mut W {
280        const MASK: bool = true;
281        const OFFSET: u8 = 10;
282        self.w.bits &= !((MASK as u32) << OFFSET);
283        self.w.bits |= ((value & MASK) as u32) << OFFSET;
284        self.w
285    }
286}
287#[doc = r" Proxy"]
288pub struct _ICRSTW<'a> {
289    w: &'a mut W,
290}
291impl<'a> _ICRSTW<'a> {
292    #[doc = r" Sets the field bit"]
293    pub fn set_bit(self) -> &'a mut W {
294        self.bit(true)
295    }
296    #[doc = r" Clears the field bit"]
297    pub fn clear_bit(self) -> &'a mut W {
298        self.bit(false)
299    }
300    #[doc = r" Writes raw bits to the field"]
301    #[inline]
302    pub fn bit(self, value: bool) -> &'a mut W {
303        const MASK: bool = true;
304        const OFFSET: u8 = 11;
305        self.w.bits &= !((MASK as u32) << OFFSET);
306        self.w.bits |= ((value & MASK) as u32) << OFFSET;
307        self.w
308    }
309}
310#[doc = r" Proxy"]
311pub struct _DCRSTW<'a> {
312    w: &'a mut W,
313}
314impl<'a> _DCRSTW<'a> {
315    #[doc = r" Sets the field bit"]
316    pub fn set_bit(self) -> &'a mut W {
317        self.bit(true)
318    }
319    #[doc = r" Clears the field bit"]
320    pub fn clear_bit(self) -> &'a mut W {
321        self.bit(false)
322    }
323    #[doc = r" Writes raw bits to the field"]
324    #[inline]
325    pub fn bit(self, value: bool) -> &'a mut W {
326        const MASK: bool = true;
327        const OFFSET: u8 = 12;
328        self.w.bits &= !((MASK as u32) << OFFSET);
329        self.w.bits |= ((value & MASK) as u32) << OFFSET;
330        self.w
331    }
332}
333#[doc = r" Proxy"]
334pub struct _RUN_PDW<'a> {
335    w: &'a mut W,
336}
337impl<'a> _RUN_PDW<'a> {
338    #[doc = r" Sets the field bit"]
339    pub fn set_bit(self) -> &'a mut W {
340        self.bit(true)
341    }
342    #[doc = r" Clears the field bit"]
343    pub fn clear_bit(self) -> &'a mut W {
344        self.bit(false)
345    }
346    #[doc = r" Writes raw bits to the field"]
347    #[inline]
348    pub fn bit(self, value: bool) -> &'a mut W {
349        const MASK: bool = true;
350        const OFFSET: u8 = 13;
351        self.w.bits &= !((MASK as u32) << OFFSET);
352        self.w.bits |= ((value & MASK) as u32) << OFFSET;
353        self.w
354    }
355}
356#[doc = r" Proxy"]
357pub struct _SLEEP_PDW<'a> {
358    w: &'a mut W,
359}
360impl<'a> _SLEEP_PDW<'a> {
361    #[doc = r" Sets the field bit"]
362    pub fn set_bit(self) -> &'a mut W {
363        self.bit(true)
364    }
365    #[doc = r" Clears the field bit"]
366    pub fn clear_bit(self) -> &'a mut W {
367        self.bit(false)
368    }
369    #[doc = r" Writes raw bits to the field"]
370    #[inline]
371    pub fn bit(self, value: bool) -> &'a mut W {
372        const MASK: bool = true;
373        const OFFSET: u8 = 14;
374        self.w.bits &= !((MASK as u32) << OFFSET);
375        self.w.bits |= ((value & MASK) as u32) << OFFSET;
376        self.w
377    }
378}
379impl R {
380    #[doc = r" Value of the register as raw bits"]
381    #[inline]
382    pub fn bits(&self) -> u32 {
383        self.bits
384    }
385    #[doc = "Bits 0:2 - Latency"]
386    #[inline]
387    pub fn latency(&self) -> LATENCYR {
388        let bits = {
389            const MASK: u8 = 7;
390            const OFFSET: u8 = 0;
391            ((self.bits >> OFFSET) & MASK as u32) as u8
392        };
393        LATENCYR { bits }
394    }
395    #[doc = "Bit 8 - Prefetch enable"]
396    #[inline]
397    pub fn prften(&self) -> PRFTENR {
398        let bits = {
399            const MASK: bool = true;
400            const OFFSET: u8 = 8;
401            ((self.bits >> OFFSET) & MASK as u32) != 0
402        };
403        PRFTENR { bits }
404    }
405    #[doc = "Bit 9 - Instruction cache enable"]
406    #[inline]
407    pub fn icen(&self) -> ICENR {
408        let bits = {
409            const MASK: bool = true;
410            const OFFSET: u8 = 9;
411            ((self.bits >> OFFSET) & MASK as u32) != 0
412        };
413        ICENR { bits }
414    }
415    #[doc = "Bit 10 - Data cache enable"]
416    #[inline]
417    pub fn dcen(&self) -> DCENR {
418        let bits = {
419            const MASK: bool = true;
420            const OFFSET: u8 = 10;
421            ((self.bits >> OFFSET) & MASK as u32) != 0
422        };
423        DCENR { bits }
424    }
425    #[doc = "Bit 11 - Instruction cache reset"]
426    #[inline]
427    pub fn icrst(&self) -> ICRSTR {
428        let bits = {
429            const MASK: bool = true;
430            const OFFSET: u8 = 11;
431            ((self.bits >> OFFSET) & MASK as u32) != 0
432        };
433        ICRSTR { bits }
434    }
435    #[doc = "Bit 12 - Data cache reset"]
436    #[inline]
437    pub fn dcrst(&self) -> DCRSTR {
438        let bits = {
439            const MASK: bool = true;
440            const OFFSET: u8 = 12;
441            ((self.bits >> OFFSET) & MASK as u32) != 0
442        };
443        DCRSTR { bits }
444    }
445    #[doc = "Bit 13 - Flash Power-down mode during Low-power run mode"]
446    #[inline]
447    pub fn run_pd(&self) -> RUN_PDR {
448        let bits = {
449            const MASK: bool = true;
450            const OFFSET: u8 = 13;
451            ((self.bits >> OFFSET) & MASK as u32) != 0
452        };
453        RUN_PDR { bits }
454    }
455    #[doc = "Bit 14 - Flash Power-down mode during Low-power sleep mode"]
456    #[inline]
457    pub fn sleep_pd(&self) -> SLEEP_PDR {
458        let bits = {
459            const MASK: bool = true;
460            const OFFSET: u8 = 14;
461            ((self.bits >> OFFSET) & MASK as u32) != 0
462        };
463        SLEEP_PDR { bits }
464    }
465}
466impl W {
467    #[doc = r" Reset value of the register"]
468    #[inline]
469    pub fn reset_value() -> W {
470        W { bits: 1536 }
471    }
472    #[doc = r" Writes raw bits to the register"]
473    #[inline]
474    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
475        self.bits = bits;
476        self
477    }
478    #[doc = "Bits 0:2 - Latency"]
479    #[inline]
480    pub fn latency(&mut self) -> _LATENCYW {
481        _LATENCYW { w: self }
482    }
483    #[doc = "Bit 8 - Prefetch enable"]
484    #[inline]
485    pub fn prften(&mut self) -> _PRFTENW {
486        _PRFTENW { w: self }
487    }
488    #[doc = "Bit 9 - Instruction cache enable"]
489    #[inline]
490    pub fn icen(&mut self) -> _ICENW {
491        _ICENW { w: self }
492    }
493    #[doc = "Bit 10 - Data cache enable"]
494    #[inline]
495    pub fn dcen(&mut self) -> _DCENW {
496        _DCENW { w: self }
497    }
498    #[doc = "Bit 11 - Instruction cache reset"]
499    #[inline]
500    pub fn icrst(&mut self) -> _ICRSTW {
501        _ICRSTW { w: self }
502    }
503    #[doc = "Bit 12 - Data cache reset"]
504    #[inline]
505    pub fn dcrst(&mut self) -> _DCRSTW {
506        _DCRSTW { w: self }
507    }
508    #[doc = "Bit 13 - Flash Power-down mode during Low-power run mode"]
509    #[inline]
510    pub fn run_pd(&mut self) -> _RUN_PDW {
511        _RUN_PDW { w: self }
512    }
513    #[doc = "Bit 14 - Flash Power-down mode during Low-power sleep mode"]
514    #[inline]
515    pub fn sleep_pd(&mut self) -> _SLEEP_PDW {
516        _SLEEP_PDW { w: self }
517    }
518}
stm32l4x2_pac/flash/acr.rs

stm32l4x2_pac/flash/
acr.rs
