stm32l4x2_pac/crs/
cfgr.rs

1#[doc = r" Value read from the register"]
2pub struct R {
3    bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7    bits: u32,
8}
9impl super::CFGR {
10    #[doc = r" Modifies the contents of the register"]
11    #[inline]
12    pub fn modify<F>(&self, f: F)
13    where
14        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15    {
16        let bits = self.register.get();
17        let r = R { bits: bits };
18        let mut w = W { bits: bits };
19        f(&r, &mut w);
20        self.register.set(w.bits);
21    }
22    #[doc = r" Reads the contents of the register"]
23    #[inline]
24    pub fn read(&self) -> R {
25        R {
26            bits: self.register.get(),
27        }
28    }
29    #[doc = r" Writes to the register"]
30    #[inline]
31    pub fn write<F>(&self, f: F)
32    where
33        F: FnOnce(&mut W) -> &mut W,
34    {
35        let mut w = W::reset_value();
36        f(&mut w);
37        self.register.set(w.bits);
38    }
39    #[doc = r" Writes the reset value to the register"]
40    #[inline]
41    pub fn reset(&self) {
42        self.write(|w| w)
43    }
44}
45#[doc = r" Value of the field"]
46pub struct SYNCPOLR {
47    bits: bool,
48}
49impl SYNCPOLR {
50    #[doc = r" Value of the field as raw bits"]
51    #[inline]
52    pub fn bit(&self) -> bool {
53        self.bits
54    }
55    #[doc = r" Returns `true` if the bit is clear (0)"]
56    #[inline]
57    pub fn bit_is_clear(&self) -> bool {
58        !self.bit()
59    }
60    #[doc = r" Returns `true` if the bit is set (1)"]
61    #[inline]
62    pub fn bit_is_set(&self) -> bool {
63        self.bit()
64    }
65}
66#[doc = r" Value of the field"]
67pub struct SYNCSRCR {
68    bits: u8,
69}
70impl SYNCSRCR {
71    #[doc = r" Value of the field as raw bits"]
72    #[inline]
73    pub fn bits(&self) -> u8 {
74        self.bits
75    }
76}
77#[doc = r" Value of the field"]
78pub struct SYNCDIVR {
79    bits: u8,
80}
81impl SYNCDIVR {
82    #[doc = r" Value of the field as raw bits"]
83    #[inline]
84    pub fn bits(&self) -> u8 {
85        self.bits
86    }
87}
88#[doc = r" Value of the field"]
89pub struct FELIMR {
90    bits: u8,
91}
92impl FELIMR {
93    #[doc = r" Value of the field as raw bits"]
94    #[inline]
95    pub fn bits(&self) -> u8 {
96        self.bits
97    }
98}
99#[doc = r" Value of the field"]
100pub struct RELOADR {
101    bits: u16,
102}
103impl RELOADR {
104    #[doc = r" Value of the field as raw bits"]
105    #[inline]
106    pub fn bits(&self) -> u16 {
107        self.bits
108    }
109}
110#[doc = r" Proxy"]
111pub struct _SYNCPOLW<'a> {
112    w: &'a mut W,
113}
114impl<'a> _SYNCPOLW<'a> {
115    #[doc = r" Sets the field bit"]
116    pub fn set_bit(self) -> &'a mut W {
117        self.bit(true)
118    }
119    #[doc = r" Clears the field bit"]
120    pub fn clear_bit(self) -> &'a mut W {
121        self.bit(false)
122    }
123    #[doc = r" Writes raw bits to the field"]
124    #[inline]
125    pub fn bit(self, value: bool) -> &'a mut W {
126        const MASK: bool = true;
127        const OFFSET: u8 = 31;
128        self.w.bits &= !((MASK as u32) << OFFSET);
129        self.w.bits |= ((value & MASK) as u32) << OFFSET;
130        self.w
131    }
132}
133#[doc = r" Proxy"]
134pub struct _SYNCSRCW<'a> {
135    w: &'a mut W,
136}
137impl<'a> _SYNCSRCW<'a> {
138    #[doc = r" Writes raw bits to the field"]
139    #[inline]
140    pub unsafe fn bits(self, value: u8) -> &'a mut W {
141        const MASK: u8 = 3;
142        const OFFSET: u8 = 28;
143        self.w.bits &= !((MASK as u32) << OFFSET);
144        self.w.bits |= ((value & MASK) as u32) << OFFSET;
145        self.w
146    }
147}
148#[doc = r" Proxy"]
149pub struct _SYNCDIVW<'a> {
150    w: &'a mut W,
151}
152impl<'a> _SYNCDIVW<'a> {
153    #[doc = r" Writes raw bits to the field"]
154    #[inline]
155    pub unsafe fn bits(self, value: u8) -> &'a mut W {
156        const MASK: u8 = 7;
157        const OFFSET: u8 = 24;
158        self.w.bits &= !((MASK as u32) << OFFSET);
159        self.w.bits |= ((value & MASK) as u32) << OFFSET;
160        self.w
161    }
162}
163#[doc = r" Proxy"]
164pub struct _FELIMW<'a> {
165    w: &'a mut W,
166}
167impl<'a> _FELIMW<'a> {
168    #[doc = r" Writes raw bits to the field"]
169    #[inline]
170    pub unsafe fn bits(self, value: u8) -> &'a mut W {
171        const MASK: u8 = 255;
172        const OFFSET: u8 = 16;
173        self.w.bits &= !((MASK as u32) << OFFSET);
174        self.w.bits |= ((value & MASK) as u32) << OFFSET;
175        self.w
176    }
177}
178#[doc = r" Proxy"]
179pub struct _RELOADW<'a> {
180    w: &'a mut W,
181}
182impl<'a> _RELOADW<'a> {
183    #[doc = r" Writes raw bits to the field"]
184    #[inline]
185    pub unsafe fn bits(self, value: u16) -> &'a mut W {
186        const MASK: u16 = 65535;
187        const OFFSET: u8 = 0;
188        self.w.bits &= !((MASK as u32) << OFFSET);
189        self.w.bits |= ((value & MASK) as u32) << OFFSET;
190        self.w
191    }
192}
193impl R {
194    #[doc = r" Value of the register as raw bits"]
195    #[inline]
196    pub fn bits(&self) -> u32 {
197        self.bits
198    }
199    #[doc = "Bit 31 - SYNC polarity selection"]
200    #[inline]
201    pub fn syncpol(&self) -> SYNCPOLR {
202        let bits = {
203            const MASK: bool = true;
204            const OFFSET: u8 = 31;
205            ((self.bits >> OFFSET) & MASK as u32) != 0
206        };
207        SYNCPOLR { bits }
208    }
209    #[doc = "Bits 28:29 - SYNC signal source selection"]
210    #[inline]
211    pub fn syncsrc(&self) -> SYNCSRCR {
212        let bits = {
213            const MASK: u8 = 3;
214            const OFFSET: u8 = 28;
215            ((self.bits >> OFFSET) & MASK as u32) as u8
216        };
217        SYNCSRCR { bits }
218    }
219    #[doc = "Bits 24:26 - SYNC divider"]
220    #[inline]
221    pub fn syncdiv(&self) -> SYNCDIVR {
222        let bits = {
223            const MASK: u8 = 7;
224            const OFFSET: u8 = 24;
225            ((self.bits >> OFFSET) & MASK as u32) as u8
226        };
227        SYNCDIVR { bits }
228    }
229    #[doc = "Bits 16:23 - Frequency error limit"]
230    #[inline]
231    pub fn felim(&self) -> FELIMR {
232        let bits = {
233            const MASK: u8 = 255;
234            const OFFSET: u8 = 16;
235            ((self.bits >> OFFSET) & MASK as u32) as u8
236        };
237        FELIMR { bits }
238    }
239    #[doc = "Bits 0:15 - Counter reload value"]
240    #[inline]
241    pub fn reload(&self) -> RELOADR {
242        let bits = {
243            const MASK: u16 = 65535;
244            const OFFSET: u8 = 0;
245            ((self.bits >> OFFSET) & MASK as u32) as u16
246        };
247        RELOADR { bits }
248    }
249}
250impl W {
251    #[doc = r" Reset value of the register"]
252    #[inline]
253    pub fn reset_value() -> W {
254        W { bits: 539147135 }
255    }
256    #[doc = r" Writes raw bits to the register"]
257    #[inline]
258    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
259        self.bits = bits;
260        self
261    }
262    #[doc = "Bit 31 - SYNC polarity selection"]
263    #[inline]
264    pub fn syncpol(&mut self) -> _SYNCPOLW {
265        _SYNCPOLW { w: self }
266    }
267    #[doc = "Bits 28:29 - SYNC signal source selection"]
268    #[inline]
269    pub fn syncsrc(&mut self) -> _SYNCSRCW {
270        _SYNCSRCW { w: self }
271    }
272    #[doc = "Bits 24:26 - SYNC divider"]
273    #[inline]
274    pub fn syncdiv(&mut self) -> _SYNCDIVW {
275        _SYNCDIVW { w: self }
276    }
277    #[doc = "Bits 16:23 - Frequency error limit"]
278    #[inline]
279    pub fn felim(&mut self) -> _FELIMW {
280        _FELIMW { w: self }
281    }
282    #[doc = "Bits 0:15 - Counter reload value"]
283    #[inline]
284    pub fn reload(&mut self) -> _RELOADW {
285        _RELOADW { w: self }
286    }
287}
stm32l4x2_pac/crs/cfgr.rs

stm32l4x2_pac/crs/
cfgr.rs
