stm32l4x2_pac/
can1.rs

1#[doc = r" Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4    #[doc = "0x00 - master control register"]
5    pub mcr: MCR,
6    #[doc = "0x04 - master status register"]
7    pub msr: MSR,
8    #[doc = "0x08 - transmit status register"]
9    pub tsr: TSR,
10    #[doc = "0x0c - receive FIFO 0 register"]
11    pub rfr: [RFR; 2],
12    #[doc = "0x14 - interrupt enable register"]
13    pub ier: IER,
14    #[doc = "0x18 - interrupt enable register"]
15    pub esr: ESR,
16    #[doc = "0x1c - bit timing register"]
17    pub btr: BTR,
18    _reserved0: [u8; 352usize],
19    #[doc = "0x180 - CAN Transmit cluster"]
20    pub tx: [TX; 3],
21    #[doc = "0x1b0 - CAN Receive cluster"]
22    pub rx: [RX; 2],
23    _reserved1: [u8; 48usize],
24    #[doc = "0x200 - filter master register"]
25    pub fmr: FMR,
26    #[doc = "0x204 - filter mode register"]
27    pub fm1r: FM1R,
28    _reserved2: [u8; 4usize],
29    #[doc = "0x20c - filter scale register"]
30    pub fs1r: FS1R,
31    _reserved3: [u8; 4usize],
32    #[doc = "0x214 - filter FIFO assignment register"]
33    pub ffa1r: FFA1R,
34    _reserved4: [u8; 4usize],
35    #[doc = "0x21c - filter activation register"]
36    pub fa1r: FA1R,
37    _reserved5: [u8; 32usize],
38    #[doc = "0x240 - CAN Filter Bank cluster"]
39    pub fb: [FB; 28],
40}
41#[doc = r" Register block"]
42#[repr(C)]
43pub struct TX {
44    #[doc = "0x00 - TX mailbox identifier register"]
45    pub tir: self::tx::TIR,
46    #[doc = "0x04 - mailbox data length control and time stamp register"]
47    pub tdtr: self::tx::TDTR,
48    #[doc = "0x08 - mailbox data low register"]
49    pub tdlr: self::tx::TDLR,
50    #[doc = "0x0c - mailbox data high register"]
51    pub tdhr: self::tx::TDHR,
52}
53#[doc = r" Register block"]
54#[doc = "CAN Transmit cluster"]
55pub mod tx;
56#[doc = r" Register block"]
57#[repr(C)]
58pub struct RX {
59    #[doc = "0x00 - receive FIFO mailbox identifier register"]
60    pub rir: self::rx::RIR,
61    #[doc = "0x04 - mailbox data high register"]
62    pub rdtr: self::rx::RDTR,
63    #[doc = "0x08 - mailbox data high register"]
64    pub rdlr: self::rx::RDLR,
65    #[doc = "0x0c - receive FIFO mailbox data high register"]
66    pub rdhr: self::rx::RDHR,
67}
68#[doc = r" Register block"]
69#[doc = "CAN Receive cluster"]
70pub mod rx;
71#[doc = r" Register block"]
72#[repr(C)]
73pub struct FB {
74    #[doc = "0x00 - Filter bank 0 register 1"]
75    pub fr1: self::fb::FR1,
76    #[doc = "0x04 - Filter bank 0 register 2"]
77    pub fr2: self::fb::FR2,
78}
79#[doc = r" Register block"]
80#[doc = "CAN Filter Bank cluster"]
81pub mod fb;
82#[doc = "master control register"]
83pub struct MCR {
84    register: ::vcell::VolatileCell<u32>,
85}
86#[doc = "master control register"]
87pub mod mcr;
88#[doc = "master status register"]
89pub struct MSR {
90    register: ::vcell::VolatileCell<u32>,
91}
92#[doc = "master status register"]
93pub mod msr;
94#[doc = "transmit status register"]
95pub struct TSR {
96    register: ::vcell::VolatileCell<u32>,
97}
98#[doc = "transmit status register"]
99pub mod tsr;
100#[doc = "receive FIFO 0 register"]
101pub struct RFR {
102    register: ::vcell::VolatileCell<u32>,
103}
104#[doc = "receive FIFO 0 register"]
105pub mod rfr;
106#[doc = "interrupt enable register"]
107pub struct IER {
108    register: ::vcell::VolatileCell<u32>,
109}
110#[doc = "interrupt enable register"]
111pub mod ier;
112#[doc = "interrupt enable register"]
113pub struct ESR {
114    register: ::vcell::VolatileCell<u32>,
115}
116#[doc = "interrupt enable register"]
117pub mod esr;
118#[doc = "bit timing register"]
119pub struct BTR {
120    register: ::vcell::VolatileCell<u32>,
121}
122#[doc = "bit timing register"]
123pub mod btr;
124#[doc = "filter master register"]
125pub struct FMR {
126    register: ::vcell::VolatileCell<u32>,
127}
128#[doc = "filter master register"]
129pub mod fmr;
130#[doc = "filter mode register"]
131pub struct FM1R {
132    register: ::vcell::VolatileCell<u32>,
133}
134#[doc = "filter mode register"]
135pub mod fm1r;
136#[doc = "filter scale register"]
137pub struct FS1R {
138    register: ::vcell::VolatileCell<u32>,
139}
140#[doc = "filter scale register"]
141pub mod fs1r;
142#[doc = "filter FIFO assignment register"]
143pub struct FFA1R {
144    register: ::vcell::VolatileCell<u32>,
145}
146#[doc = "filter FIFO assignment register"]
147pub mod ffa1r;
148#[doc = "filter activation register"]
149pub struct FA1R {
150    register: ::vcell::VolatileCell<u32>,
151}
152#[doc = "filter activation register"]
153pub mod fa1r;
stm32l4x2_pac/can1.rs

stm32l4x2_pac/
can1.rs
