stm32l476/tim2/
ccmr1_output.rs

1#[doc = "Register `CCMR1_Output` reader"]
2pub type R = crate::R<Ccmr1OutputSpec>;
3#[doc = "Register `CCMR1_Output` writer"]
4pub type W = crate::W<Ccmr1OutputSpec>;
5#[doc = "Field `CC1S` reader - Capture/Compare 1 selection"]
6pub type Cc1sR = crate::FieldReader;
7#[doc = "Field `CC1S` writer - Capture/Compare 1 selection"]
8pub type Cc1sW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `OC1FE` reader - Output compare 1 fast enable"]
10pub type Oc1feR = crate::BitReader;
11#[doc = "Field `OC1FE` writer - Output compare 1 fast enable"]
12pub type Oc1feW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `OC1PE` reader - Output compare 1 preload enable"]
14pub type Oc1peR = crate::BitReader;
15#[doc = "Field `OC1PE` writer - Output compare 1 preload enable"]
16pub type Oc1peW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `OC1M` reader - Output compare 1 mode"]
18pub type Oc1mR = crate::FieldReader;
19#[doc = "Field `OC1M` writer - Output compare 1 mode"]
20pub type Oc1mW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
21#[doc = "Field `OC1CE` reader - Output compare 1 clear enable"]
22pub type Oc1ceR = crate::BitReader;
23#[doc = "Field `OC1CE` writer - Output compare 1 clear enable"]
24pub type Oc1ceW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `CC2S` reader - Capture/Compare 2 selection"]
26pub type Cc2sR = crate::FieldReader;
27#[doc = "Field `CC2S` writer - Capture/Compare 2 selection"]
28pub type Cc2sW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
29#[doc = "Field `OC2FE` reader - Output compare 2 fast enable"]
30pub type Oc2feR = crate::BitReader;
31#[doc = "Field `OC2FE` writer - Output compare 2 fast enable"]
32pub type Oc2feW<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `OC2PE` reader - Output compare 2 preload enable"]
34pub type Oc2peR = crate::BitReader;
35#[doc = "Field `OC2PE` writer - Output compare 2 preload enable"]
36pub type Oc2peW<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `OC2M` reader - Output compare 2 mode"]
38pub type Oc2mR = crate::FieldReader;
39#[doc = "Field `OC2M` writer - Output compare 2 mode"]
40pub type Oc2mW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
41#[doc = "Field `OC2CE` reader - Output compare 2 clear enable"]
42pub type Oc2ceR = crate::BitReader;
43#[doc = "Field `OC2CE` writer - Output compare 2 clear enable"]
44pub type Oc2ceW<'a, REG> = crate::BitWriter<'a, REG>;
45impl R {
46    #[doc = "Bits 0:1 - Capture/Compare 1 selection"]
47    #[inline(always)]
48    pub fn cc1s(&self) -> Cc1sR {
49        Cc1sR::new((self.bits & 3) as u8)
50    }
51    #[doc = "Bit 2 - Output compare 1 fast enable"]
52    #[inline(always)]
53    pub fn oc1fe(&self) -> Oc1feR {
54        Oc1feR::new(((self.bits >> 2) & 1) != 0)
55    }
56    #[doc = "Bit 3 - Output compare 1 preload enable"]
57    #[inline(always)]
58    pub fn oc1pe(&self) -> Oc1peR {
59        Oc1peR::new(((self.bits >> 3) & 1) != 0)
60    }
61    #[doc = "Bits 4:6 - Output compare 1 mode"]
62    #[inline(always)]
63    pub fn oc1m(&self) -> Oc1mR {
64        Oc1mR::new(((self.bits >> 4) & 7) as u8)
65    }
66    #[doc = "Bit 7 - Output compare 1 clear enable"]
67    #[inline(always)]
68    pub fn oc1ce(&self) -> Oc1ceR {
69        Oc1ceR::new(((self.bits >> 7) & 1) != 0)
70    }
71    #[doc = "Bits 8:9 - Capture/Compare 2 selection"]
72    #[inline(always)]
73    pub fn cc2s(&self) -> Cc2sR {
74        Cc2sR::new(((self.bits >> 8) & 3) as u8)
75    }
76    #[doc = "Bit 10 - Output compare 2 fast enable"]
77    #[inline(always)]
78    pub fn oc2fe(&self) -> Oc2feR {
79        Oc2feR::new(((self.bits >> 10) & 1) != 0)
80    }
81    #[doc = "Bit 11 - Output compare 2 preload enable"]
82    #[inline(always)]
83    pub fn oc2pe(&self) -> Oc2peR {
84        Oc2peR::new(((self.bits >> 11) & 1) != 0)
85    }
86    #[doc = "Bits 12:14 - Output compare 2 mode"]
87    #[inline(always)]
88    pub fn oc2m(&self) -> Oc2mR {
89        Oc2mR::new(((self.bits >> 12) & 7) as u8)
90    }
91    #[doc = "Bit 15 - Output compare 2 clear enable"]
92    #[inline(always)]
93    pub fn oc2ce(&self) -> Oc2ceR {
94        Oc2ceR::new(((self.bits >> 15) & 1) != 0)
95    }
96}
97impl W {
98    #[doc = "Bits 0:1 - Capture/Compare 1 selection"]
99    #[inline(always)]
100    pub fn cc1s(&mut self) -> Cc1sW<Ccmr1OutputSpec> {
101        Cc1sW::new(self, 0)
102    }
103    #[doc = "Bit 2 - Output compare 1 fast enable"]
104    #[inline(always)]
105    pub fn oc1fe(&mut self) -> Oc1feW<Ccmr1OutputSpec> {
106        Oc1feW::new(self, 2)
107    }
108    #[doc = "Bit 3 - Output compare 1 preload enable"]
109    #[inline(always)]
110    pub fn oc1pe(&mut self) -> Oc1peW<Ccmr1OutputSpec> {
111        Oc1peW::new(self, 3)
112    }
113    #[doc = "Bits 4:6 - Output compare 1 mode"]
114    #[inline(always)]
115    pub fn oc1m(&mut self) -> Oc1mW<Ccmr1OutputSpec> {
116        Oc1mW::new(self, 4)
117    }
118    #[doc = "Bit 7 - Output compare 1 clear enable"]
119    #[inline(always)]
120    pub fn oc1ce(&mut self) -> Oc1ceW<Ccmr1OutputSpec> {
121        Oc1ceW::new(self, 7)
122    }
123    #[doc = "Bits 8:9 - Capture/Compare 2 selection"]
124    #[inline(always)]
125    pub fn cc2s(&mut self) -> Cc2sW<Ccmr1OutputSpec> {
126        Cc2sW::new(self, 8)
127    }
128    #[doc = "Bit 10 - Output compare 2 fast enable"]
129    #[inline(always)]
130    pub fn oc2fe(&mut self) -> Oc2feW<Ccmr1OutputSpec> {
131        Oc2feW::new(self, 10)
132    }
133    #[doc = "Bit 11 - Output compare 2 preload enable"]
134    #[inline(always)]
135    pub fn oc2pe(&mut self) -> Oc2peW<Ccmr1OutputSpec> {
136        Oc2peW::new(self, 11)
137    }
138    #[doc = "Bits 12:14 - Output compare 2 mode"]
139    #[inline(always)]
140    pub fn oc2m(&mut self) -> Oc2mW<Ccmr1OutputSpec> {
141        Oc2mW::new(self, 12)
142    }
143    #[doc = "Bit 15 - Output compare 2 clear enable"]
144    #[inline(always)]
145    pub fn oc2ce(&mut self) -> Oc2ceW<Ccmr1OutputSpec> {
146        Oc2ceW::new(self, 15)
147    }
148}
149#[doc = "capture/compare mode register 1 (output mode)\n\nYou can [`read`](crate::Reg::read) this register and get [`ccmr1_output::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_output::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
150pub struct Ccmr1OutputSpec;
151impl crate::RegisterSpec for Ccmr1OutputSpec {
152    type Ux = u32;
153}
154#[doc = "`read()` method returns [`ccmr1_output::R`](R) reader structure"]
155impl crate::Readable for Ccmr1OutputSpec {}
156#[doc = "`write(|w| ..)` method takes [`ccmr1_output::W`](W) writer structure"]
157impl crate::Writable for Ccmr1OutputSpec {
158    type Safety = crate::Unsafe;
159}
160#[doc = "`reset()` method sets CCMR1_Output to value 0"]
161impl crate::Resettable for Ccmr1OutputSpec {}
stm32l476/tim2/ccmr1_output.rs

stm32l476/tim2/
ccmr1_output.rs
