stm32l476/sai1/
bcr1.rs

1#[doc = "Register `BCR1` reader"]
2pub type R = crate::R<Bcr1Spec>;
3#[doc = "Register `BCR1` writer"]
4pub type W = crate::W<Bcr1Spec>;
5#[doc = "Field `MODE` reader - Audio block mode"]
6pub type ModeR = crate::FieldReader;
7#[doc = "Field `MODE` writer - Audio block mode"]
8pub type ModeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `PRTCFG` reader - Protocol configuration"]
10pub type PrtcfgR = crate::FieldReader;
11#[doc = "Field `PRTCFG` writer - Protocol configuration"]
12pub type PrtcfgW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13#[doc = "Field `DS` reader - Data size"]
14pub type DsR = crate::FieldReader;
15#[doc = "Field `DS` writer - Data size"]
16pub type DsW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
17#[doc = "Field `LSBFIRST` reader - Least significant bit first"]
18pub type LsbfirstR = crate::BitReader;
19#[doc = "Field `LSBFIRST` writer - Least significant bit first"]
20pub type LsbfirstW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `CKSTR` reader - Clock strobing edge"]
22pub type CkstrR = crate::BitReader;
23#[doc = "Field `CKSTR` writer - Clock strobing edge"]
24pub type CkstrW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `SYNCEN` reader - Synchronization enable"]
26pub type SyncenR = crate::FieldReader;
27#[doc = "Field `SYNCEN` writer - Synchronization enable"]
28pub type SyncenW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
29#[doc = "Field `MONO` reader - Mono mode"]
30pub type MonoR = crate::BitReader;
31#[doc = "Field `MONO` writer - Mono mode"]
32pub type MonoW<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `OutDri` reader - Output drive"]
34pub type OutDriR = crate::BitReader;
35#[doc = "Field `OutDri` writer - Output drive"]
36pub type OutDriW<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `SAIBEN` reader - Audio block B enable"]
38pub type SaibenR = crate::BitReader;
39#[doc = "Field `SAIBEN` writer - Audio block B enable"]
40pub type SaibenW<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `DMAEN` reader - DMA enable"]
42pub type DmaenR = crate::BitReader;
43#[doc = "Field `DMAEN` writer - DMA enable"]
44pub type DmaenW<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `NODIV` reader - No divider"]
46pub type NodivR = crate::BitReader;
47#[doc = "Field `NODIV` writer - No divider"]
48pub type NodivW<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `MCKDIV` reader - Master clock divider"]
50pub type MckdivR = crate::FieldReader;
51#[doc = "Field `MCKDIV` writer - Master clock divider"]
52pub type MckdivW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
53impl R {
54    #[doc = "Bits 0:1 - Audio block mode"]
55    #[inline(always)]
56    pub fn mode(&self) -> ModeR {
57        ModeR::new((self.bits & 3) as u8)
58    }
59    #[doc = "Bits 2:3 - Protocol configuration"]
60    #[inline(always)]
61    pub fn prtcfg(&self) -> PrtcfgR {
62        PrtcfgR::new(((self.bits >> 2) & 3) as u8)
63    }
64    #[doc = "Bits 5:7 - Data size"]
65    #[inline(always)]
66    pub fn ds(&self) -> DsR {
67        DsR::new(((self.bits >> 5) & 7) as u8)
68    }
69    #[doc = "Bit 8 - Least significant bit first"]
70    #[inline(always)]
71    pub fn lsbfirst(&self) -> LsbfirstR {
72        LsbfirstR::new(((self.bits >> 8) & 1) != 0)
73    }
74    #[doc = "Bit 9 - Clock strobing edge"]
75    #[inline(always)]
76    pub fn ckstr(&self) -> CkstrR {
77        CkstrR::new(((self.bits >> 9) & 1) != 0)
78    }
79    #[doc = "Bits 10:11 - Synchronization enable"]
80    #[inline(always)]
81    pub fn syncen(&self) -> SyncenR {
82        SyncenR::new(((self.bits >> 10) & 3) as u8)
83    }
84    #[doc = "Bit 12 - Mono mode"]
85    #[inline(always)]
86    pub fn mono(&self) -> MonoR {
87        MonoR::new(((self.bits >> 12) & 1) != 0)
88    }
89    #[doc = "Bit 13 - Output drive"]
90    #[inline(always)]
91    pub fn out_dri(&self) -> OutDriR {
92        OutDriR::new(((self.bits >> 13) & 1) != 0)
93    }
94    #[doc = "Bit 16 - Audio block B enable"]
95    #[inline(always)]
96    pub fn saiben(&self) -> SaibenR {
97        SaibenR::new(((self.bits >> 16) & 1) != 0)
98    }
99    #[doc = "Bit 17 - DMA enable"]
100    #[inline(always)]
101    pub fn dmaen(&self) -> DmaenR {
102        DmaenR::new(((self.bits >> 17) & 1) != 0)
103    }
104    #[doc = "Bit 19 - No divider"]
105    #[inline(always)]
106    pub fn nodiv(&self) -> NodivR {
107        NodivR::new(((self.bits >> 19) & 1) != 0)
108    }
109    #[doc = "Bits 20:23 - Master clock divider"]
110    #[inline(always)]
111    pub fn mckdiv(&self) -> MckdivR {
112        MckdivR::new(((self.bits >> 20) & 0x0f) as u8)
113    }
114}
115impl W {
116    #[doc = "Bits 0:1 - Audio block mode"]
117    #[inline(always)]
118    pub fn mode(&mut self) -> ModeW<Bcr1Spec> {
119        ModeW::new(self, 0)
120    }
121    #[doc = "Bits 2:3 - Protocol configuration"]
122    #[inline(always)]
123    pub fn prtcfg(&mut self) -> PrtcfgW<Bcr1Spec> {
124        PrtcfgW::new(self, 2)
125    }
126    #[doc = "Bits 5:7 - Data size"]
127    #[inline(always)]
128    pub fn ds(&mut self) -> DsW<Bcr1Spec> {
129        DsW::new(self, 5)
130    }
131    #[doc = "Bit 8 - Least significant bit first"]
132    #[inline(always)]
133    pub fn lsbfirst(&mut self) -> LsbfirstW<Bcr1Spec> {
134        LsbfirstW::new(self, 8)
135    }
136    #[doc = "Bit 9 - Clock strobing edge"]
137    #[inline(always)]
138    pub fn ckstr(&mut self) -> CkstrW<Bcr1Spec> {
139        CkstrW::new(self, 9)
140    }
141    #[doc = "Bits 10:11 - Synchronization enable"]
142    #[inline(always)]
143    pub fn syncen(&mut self) -> SyncenW<Bcr1Spec> {
144        SyncenW::new(self, 10)
145    }
146    #[doc = "Bit 12 - Mono mode"]
147    #[inline(always)]
148    pub fn mono(&mut self) -> MonoW<Bcr1Spec> {
149        MonoW::new(self, 12)
150    }
151    #[doc = "Bit 13 - Output drive"]
152    #[inline(always)]
153    pub fn out_dri(&mut self) -> OutDriW<Bcr1Spec> {
154        OutDriW::new(self, 13)
155    }
156    #[doc = "Bit 16 - Audio block B enable"]
157    #[inline(always)]
158    pub fn saiben(&mut self) -> SaibenW<Bcr1Spec> {
159        SaibenW::new(self, 16)
160    }
161    #[doc = "Bit 17 - DMA enable"]
162    #[inline(always)]
163    pub fn dmaen(&mut self) -> DmaenW<Bcr1Spec> {
164        DmaenW::new(self, 17)
165    }
166    #[doc = "Bit 19 - No divider"]
167    #[inline(always)]
168    pub fn nodiv(&mut self) -> NodivW<Bcr1Spec> {
169        NodivW::new(self, 19)
170    }
171    #[doc = "Bits 20:23 - Master clock divider"]
172    #[inline(always)]
173    pub fn mckdiv(&mut self) -> MckdivW<Bcr1Spec> {
174        MckdivW::new(self, 20)
175    }
176}
177#[doc = "BConfiguration register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`bcr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bcr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
178pub struct Bcr1Spec;
179impl crate::RegisterSpec for Bcr1Spec {
180    type Ux = u32;
181}
182#[doc = "`read()` method returns [`bcr1::R`](R) reader structure"]
183impl crate::Readable for Bcr1Spec {}
184#[doc = "`write(|w| ..)` method takes [`bcr1::W`](W) writer structure"]
185impl crate::Writable for Bcr1Spec {
186    type Safety = crate::Unsafe;
187}
188#[doc = "`reset()` method sets BCR1 to value 0x40"]
189impl crate::Resettable for Bcr1Spec {
190    const RESET_VALUE: u32 = 0x40;
191}
stm32l476/sai1/bcr1.rs

stm32l476/sai1/
bcr1.rs
