stm32l476/dfsdm1/
dfsdm_flt0cr1.rs1#[doc = "Register `DFSDM_FLT0CR1` reader"]
2pub type R = crate::R<DfsdmFlt0cr1Spec>;
3#[doc = "Register `DFSDM_FLT0CR1` writer"]
4pub type W = crate::W<DfsdmFlt0cr1Spec>;
5#[doc = "Field `DFEN` reader - DFSDM enable"]
6pub type DfenR = crate::BitReader;
7#[doc = "Field `DFEN` writer - DFSDM enable"]
8pub type DfenW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `JSWSTART` reader - Start a conversion of the injected group of channels"]
10pub type JswstartR = crate::BitReader;
11#[doc = "Field `JSWSTART` writer - Start a conversion of the injected group of channels"]
12pub type JswstartW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `JSYNC` reader - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger"]
14pub type JsyncR = crate::BitReader;
15#[doc = "Field `JSYNC` writer - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger"]
16pub type JsyncW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `JSCAN` reader - Scanning conversion mode for injected conversions"]
18pub type JscanR = crate::BitReader;
19#[doc = "Field `JSCAN` writer - Scanning conversion mode for injected conversions"]
20pub type JscanW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `JDMAEN` reader - DMA channel enabled to read data for the injected channel group"]
22pub type JdmaenR = crate::BitReader;
23#[doc = "Field `JDMAEN` writer - DMA channel enabled to read data for the injected channel group"]
24pub type JdmaenW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `JEXTSEL` reader - Trigger signal selection for launching injected conversions"]
26pub type JextselR = crate::FieldReader;
27#[doc = "Field `JEXTSEL` writer - Trigger signal selection for launching injected conversions"]
28pub type JextselW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
29#[doc = "Field `JEXTEN` reader - Trigger enable and trigger edge selection for injected conversions"]
30pub type JextenR = crate::FieldReader;
31#[doc = "Field `JEXTEN` writer - Trigger enable and trigger edge selection for injected conversions"]
32pub type JextenW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
33#[doc = "Field `RSWSTART` reader - Software start of a conversion on the regular channel"]
34pub type RswstartR = crate::BitReader;
35#[doc = "Field `RSWSTART` writer - Software start of a conversion on the regular channel"]
36pub type RswstartW<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `RCONT` reader - Continuous mode selection for regular conversions"]
38pub type RcontR = crate::BitReader;
39#[doc = "Field `RCONT` writer - Continuous mode selection for regular conversions"]
40pub type RcontW<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `RSYNC` reader - Launch regular conversion synchronously with DFSDM0"]
42pub type RsyncR = crate::BitReader;
43#[doc = "Field `RSYNC` writer - Launch regular conversion synchronously with DFSDM0"]
44pub type RsyncW<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `RDMAEN` reader - DMA channel enabled to read data for the regular conversion"]
46pub type RdmaenR = crate::BitReader;
47#[doc = "Field `RDMAEN` writer - DMA channel enabled to read data for the regular conversion"]
48pub type RdmaenW<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `RCH` reader - Regular channel selection"]
50pub type RchR = crate::FieldReader;
51#[doc = "Field `RCH` writer - Regular channel selection"]
52pub type RchW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
53#[doc = "Field `FAST` reader - Fast conversion mode selection for regular conversions"]
54pub type FastR = crate::BitReader;
55#[doc = "Field `FAST` writer - Fast conversion mode selection for regular conversions"]
56pub type FastW<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `AWFSEL` reader - Analog watchdog fast mode select"]
58pub type AwfselR = crate::BitReader;
59#[doc = "Field `AWFSEL` writer - Analog watchdog fast mode select"]
60pub type AwfselW<'a, REG> = crate::BitWriter<'a, REG>;
61impl R {
62 #[doc = "Bit 0 - DFSDM enable"]
63 #[inline(always)]
64 pub fn dfen(&self) -> DfenR {
65 DfenR::new((self.bits & 1) != 0)
66 }
67 #[doc = "Bit 1 - Start a conversion of the injected group of channels"]
68 #[inline(always)]
69 pub fn jswstart(&self) -> JswstartR {
70 JswstartR::new(((self.bits >> 1) & 1) != 0)
71 }
72 #[doc = "Bit 3 - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger"]
73 #[inline(always)]
74 pub fn jsync(&self) -> JsyncR {
75 JsyncR::new(((self.bits >> 3) & 1) != 0)
76 }
77 #[doc = "Bit 4 - Scanning conversion mode for injected conversions"]
78 #[inline(always)]
79 pub fn jscan(&self) -> JscanR {
80 JscanR::new(((self.bits >> 4) & 1) != 0)
81 }
82 #[doc = "Bit 5 - DMA channel enabled to read data for the injected channel group"]
83 #[inline(always)]
84 pub fn jdmaen(&self) -> JdmaenR {
85 JdmaenR::new(((self.bits >> 5) & 1) != 0)
86 }
87 #[doc = "Bits 8:10 - Trigger signal selection for launching injected conversions"]
88 #[inline(always)]
89 pub fn jextsel(&self) -> JextselR {
90 JextselR::new(((self.bits >> 8) & 7) as u8)
91 }
92 #[doc = "Bits 13:14 - Trigger enable and trigger edge selection for injected conversions"]
93 #[inline(always)]
94 pub fn jexten(&self) -> JextenR {
95 JextenR::new(((self.bits >> 13) & 3) as u8)
96 }
97 #[doc = "Bit 17 - Software start of a conversion on the regular channel"]
98 #[inline(always)]
99 pub fn rswstart(&self) -> RswstartR {
100 RswstartR::new(((self.bits >> 17) & 1) != 0)
101 }
102 #[doc = "Bit 18 - Continuous mode selection for regular conversions"]
103 #[inline(always)]
104 pub fn rcont(&self) -> RcontR {
105 RcontR::new(((self.bits >> 18) & 1) != 0)
106 }
107 #[doc = "Bit 19 - Launch regular conversion synchronously with DFSDM0"]
108 #[inline(always)]
109 pub fn rsync(&self) -> RsyncR {
110 RsyncR::new(((self.bits >> 19) & 1) != 0)
111 }
112 #[doc = "Bit 21 - DMA channel enabled to read data for the regular conversion"]
113 #[inline(always)]
114 pub fn rdmaen(&self) -> RdmaenR {
115 RdmaenR::new(((self.bits >> 21) & 1) != 0)
116 }
117 #[doc = "Bits 24:26 - Regular channel selection"]
118 #[inline(always)]
119 pub fn rch(&self) -> RchR {
120 RchR::new(((self.bits >> 24) & 7) as u8)
121 }
122 #[doc = "Bit 29 - Fast conversion mode selection for regular conversions"]
123 #[inline(always)]
124 pub fn fast(&self) -> FastR {
125 FastR::new(((self.bits >> 29) & 1) != 0)
126 }
127 #[doc = "Bit 30 - Analog watchdog fast mode select"]
128 #[inline(always)]
129 pub fn awfsel(&self) -> AwfselR {
130 AwfselR::new(((self.bits >> 30) & 1) != 0)
131 }
132}
133impl W {
134 #[doc = "Bit 0 - DFSDM enable"]
135 #[inline(always)]
136 pub fn dfen(&mut self) -> DfenW<DfsdmFlt0cr1Spec> {
137 DfenW::new(self, 0)
138 }
139 #[doc = "Bit 1 - Start a conversion of the injected group of channels"]
140 #[inline(always)]
141 pub fn jswstart(&mut self) -> JswstartW<DfsdmFlt0cr1Spec> {
142 JswstartW::new(self, 1)
143 }
144 #[doc = "Bit 3 - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger"]
145 #[inline(always)]
146 pub fn jsync(&mut self) -> JsyncW<DfsdmFlt0cr1Spec> {
147 JsyncW::new(self, 3)
148 }
149 #[doc = "Bit 4 - Scanning conversion mode for injected conversions"]
150 #[inline(always)]
151 pub fn jscan(&mut self) -> JscanW<DfsdmFlt0cr1Spec> {
152 JscanW::new(self, 4)
153 }
154 #[doc = "Bit 5 - DMA channel enabled to read data for the injected channel group"]
155 #[inline(always)]
156 pub fn jdmaen(&mut self) -> JdmaenW<DfsdmFlt0cr1Spec> {
157 JdmaenW::new(self, 5)
158 }
159 #[doc = "Bits 8:10 - Trigger signal selection for launching injected conversions"]
160 #[inline(always)]
161 pub fn jextsel(&mut self) -> JextselW<DfsdmFlt0cr1Spec> {
162 JextselW::new(self, 8)
163 }
164 #[doc = "Bits 13:14 - Trigger enable and trigger edge selection for injected conversions"]
165 #[inline(always)]
166 pub fn jexten(&mut self) -> JextenW<DfsdmFlt0cr1Spec> {
167 JextenW::new(self, 13)
168 }
169 #[doc = "Bit 17 - Software start of a conversion on the regular channel"]
170 #[inline(always)]
171 pub fn rswstart(&mut self) -> RswstartW<DfsdmFlt0cr1Spec> {
172 RswstartW::new(self, 17)
173 }
174 #[doc = "Bit 18 - Continuous mode selection for regular conversions"]
175 #[inline(always)]
176 pub fn rcont(&mut self) -> RcontW<DfsdmFlt0cr1Spec> {
177 RcontW::new(self, 18)
178 }
179 #[doc = "Bit 19 - Launch regular conversion synchronously with DFSDM0"]
180 #[inline(always)]
181 pub fn rsync(&mut self) -> RsyncW<DfsdmFlt0cr1Spec> {
182 RsyncW::new(self, 19)
183 }
184 #[doc = "Bit 21 - DMA channel enabled to read data for the regular conversion"]
185 #[inline(always)]
186 pub fn rdmaen(&mut self) -> RdmaenW<DfsdmFlt0cr1Spec> {
187 RdmaenW::new(self, 21)
188 }
189 #[doc = "Bits 24:26 - Regular channel selection"]
190 #[inline(always)]
191 pub fn rch(&mut self) -> RchW<DfsdmFlt0cr1Spec> {
192 RchW::new(self, 24)
193 }
194 #[doc = "Bit 29 - Fast conversion mode selection for regular conversions"]
195 #[inline(always)]
196 pub fn fast(&mut self) -> FastW<DfsdmFlt0cr1Spec> {
197 FastW::new(self, 29)
198 }
199 #[doc = "Bit 30 - Analog watchdog fast mode select"]
200 #[inline(always)]
201 pub fn awfsel(&mut self) -> AwfselW<DfsdmFlt0cr1Spec> {
202 AwfselW::new(self, 30)
203 }
204}
205#[doc = "control register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`dfsdm_flt0cr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsdm_flt0cr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
206pub struct DfsdmFlt0cr1Spec;
207impl crate::RegisterSpec for DfsdmFlt0cr1Spec {
208 type Ux = u32;
209}
210#[doc = "`read()` method returns [`dfsdm_flt0cr1::R`](R) reader structure"]
211impl crate::Readable for DfsdmFlt0cr1Spec {}
212#[doc = "`write(|w| ..)` method takes [`dfsdm_flt0cr1::W`](W) writer structure"]
213impl crate::Writable for DfsdmFlt0cr1Spec {
214 type Safety = crate::Unsafe;
215}
216#[doc = "`reset()` method sets DFSDM_FLT0CR1 to value 0"]
217impl crate::Resettable for DfsdmFlt0cr1Spec {}