stm32l476/tim8/
ccmr2_output.rs

1#[doc = "Register `CCMR2_Output` reader"]
2pub type R = crate::R<Ccmr2OutputSpec>;
3#[doc = "Register `CCMR2_Output` writer"]
4pub type W = crate::W<Ccmr2OutputSpec>;
5#[doc = "Field `CC3S` reader - Capture/Compare 3 selection"]
6pub type Cc3sR = crate::FieldReader;
7#[doc = "Field `CC3S` writer - Capture/Compare 3 selection"]
8pub type Cc3sW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `OC3FE` reader - Output compare 3 fast enable"]
10pub type Oc3feR = crate::BitReader;
11#[doc = "Field `OC3FE` writer - Output compare 3 fast enable"]
12pub type Oc3feW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `OC3PE` reader - Output compare 3 preload enable"]
14pub type Oc3peR = crate::BitReader;
15#[doc = "Field `OC3PE` writer - Output compare 3 preload enable"]
16pub type Oc3peW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `OC3M` reader - Output compare 3 mode"]
18pub type Oc3mR = crate::FieldReader;
19#[doc = "Field `OC3M` writer - Output compare 3 mode"]
20pub type Oc3mW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
21#[doc = "Field `OC3CE` reader - Output compare 3 clear enable"]
22pub type Oc3ceR = crate::BitReader;
23#[doc = "Field `OC3CE` writer - Output compare 3 clear enable"]
24pub type Oc3ceW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `CC4S` reader - Capture/Compare 4 selection"]
26pub type Cc4sR = crate::FieldReader;
27#[doc = "Field `CC4S` writer - Capture/Compare 4 selection"]
28pub type Cc4sW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
29#[doc = "Field `OC4FE` reader - Output compare 4 fast enable"]
30pub type Oc4feR = crate::BitReader;
31#[doc = "Field `OC4FE` writer - Output compare 4 fast enable"]
32pub type Oc4feW<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `OC4PE` reader - Output compare 4 preload enable"]
34pub type Oc4peR = crate::BitReader;
35#[doc = "Field `OC4PE` writer - Output compare 4 preload enable"]
36pub type Oc4peW<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `OC4M` reader - Output compare 4 mode"]
38pub type Oc4mR = crate::FieldReader;
39#[doc = "Field `OC4M` writer - Output compare 4 mode"]
40pub type Oc4mW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
41#[doc = "Field `OC4CE` reader - Output compare 4 clear enable"]
42pub type Oc4ceR = crate::BitReader;
43#[doc = "Field `OC4CE` writer - Output compare 4 clear enable"]
44pub type Oc4ceW<'a, REG> = crate::BitWriter<'a, REG>;
45impl R {
46    #[doc = "Bits 0:1 - Capture/Compare 3 selection"]
47    #[inline(always)]
48    pub fn cc3s(&self) -> Cc3sR {
49        Cc3sR::new((self.bits & 3) as u8)
50    }
51    #[doc = "Bit 2 - Output compare 3 fast enable"]
52    #[inline(always)]
53    pub fn oc3fe(&self) -> Oc3feR {
54        Oc3feR::new(((self.bits >> 2) & 1) != 0)
55    }
56    #[doc = "Bit 3 - Output compare 3 preload enable"]
57    #[inline(always)]
58    pub fn oc3pe(&self) -> Oc3peR {
59        Oc3peR::new(((self.bits >> 3) & 1) != 0)
60    }
61    #[doc = "Bits 4:6 - Output compare 3 mode"]
62    #[inline(always)]
63    pub fn oc3m(&self) -> Oc3mR {
64        Oc3mR::new(((self.bits >> 4) & 7) as u8)
65    }
66    #[doc = "Bit 7 - Output compare 3 clear enable"]
67    #[inline(always)]
68    pub fn oc3ce(&self) -> Oc3ceR {
69        Oc3ceR::new(((self.bits >> 7) & 1) != 0)
70    }
71    #[doc = "Bits 8:9 - Capture/Compare 4 selection"]
72    #[inline(always)]
73    pub fn cc4s(&self) -> Cc4sR {
74        Cc4sR::new(((self.bits >> 8) & 3) as u8)
75    }
76    #[doc = "Bit 10 - Output compare 4 fast enable"]
77    #[inline(always)]
78    pub fn oc4fe(&self) -> Oc4feR {
79        Oc4feR::new(((self.bits >> 10) & 1) != 0)
80    }
81    #[doc = "Bit 11 - Output compare 4 preload enable"]
82    #[inline(always)]
83    pub fn oc4pe(&self) -> Oc4peR {
84        Oc4peR::new(((self.bits >> 11) & 1) != 0)
85    }
86    #[doc = "Bits 12:14 - Output compare 4 mode"]
87    #[inline(always)]
88    pub fn oc4m(&self) -> Oc4mR {
89        Oc4mR::new(((self.bits >> 12) & 7) as u8)
90    }
91    #[doc = "Bit 15 - Output compare 4 clear enable"]
92    #[inline(always)]
93    pub fn oc4ce(&self) -> Oc4ceR {
94        Oc4ceR::new(((self.bits >> 15) & 1) != 0)
95    }
96}
97impl W {
98    #[doc = "Bits 0:1 - Capture/Compare 3 selection"]
99    #[inline(always)]
100    pub fn cc3s(&mut self) -> Cc3sW<Ccmr2OutputSpec> {
101        Cc3sW::new(self, 0)
102    }
103    #[doc = "Bit 2 - Output compare 3 fast enable"]
104    #[inline(always)]
105    pub fn oc3fe(&mut self) -> Oc3feW<Ccmr2OutputSpec> {
106        Oc3feW::new(self, 2)
107    }
108    #[doc = "Bit 3 - Output compare 3 preload enable"]
109    #[inline(always)]
110    pub fn oc3pe(&mut self) -> Oc3peW<Ccmr2OutputSpec> {
111        Oc3peW::new(self, 3)
112    }
113    #[doc = "Bits 4:6 - Output compare 3 mode"]
114    #[inline(always)]
115    pub fn oc3m(&mut self) -> Oc3mW<Ccmr2OutputSpec> {
116        Oc3mW::new(self, 4)
117    }
118    #[doc = "Bit 7 - Output compare 3 clear enable"]
119    #[inline(always)]
120    pub fn oc3ce(&mut self) -> Oc3ceW<Ccmr2OutputSpec> {
121        Oc3ceW::new(self, 7)
122    }
123    #[doc = "Bits 8:9 - Capture/Compare 4 selection"]
124    #[inline(always)]
125    pub fn cc4s(&mut self) -> Cc4sW<Ccmr2OutputSpec> {
126        Cc4sW::new(self, 8)
127    }
128    #[doc = "Bit 10 - Output compare 4 fast enable"]
129    #[inline(always)]
130    pub fn oc4fe(&mut self) -> Oc4feW<Ccmr2OutputSpec> {
131        Oc4feW::new(self, 10)
132    }
133    #[doc = "Bit 11 - Output compare 4 preload enable"]
134    #[inline(always)]
135    pub fn oc4pe(&mut self) -> Oc4peW<Ccmr2OutputSpec> {
136        Oc4peW::new(self, 11)
137    }
138    #[doc = "Bits 12:14 - Output compare 4 mode"]
139    #[inline(always)]
140    pub fn oc4m(&mut self) -> Oc4mW<Ccmr2OutputSpec> {
141        Oc4mW::new(self, 12)
142    }
143    #[doc = "Bit 15 - Output compare 4 clear enable"]
144    #[inline(always)]
145    pub fn oc4ce(&mut self) -> Oc4ceW<Ccmr2OutputSpec> {
146        Oc4ceW::new(self, 15)
147    }
148}
149#[doc = "capture/compare mode register 2 (output mode)\n\nYou can [`read`](crate::Reg::read) this register and get [`ccmr2_output::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr2_output::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
150pub struct Ccmr2OutputSpec;
151impl crate::RegisterSpec for Ccmr2OutputSpec {
152    type Ux = u32;
153}
154#[doc = "`read()` method returns [`ccmr2_output::R`](R) reader structure"]
155impl crate::Readable for Ccmr2OutputSpec {}
156#[doc = "`write(|w| ..)` method takes [`ccmr2_output::W`](W) writer structure"]
157impl crate::Writable for Ccmr2OutputSpec {
158    type Safety = crate::Unsafe;
159}
160#[doc = "`reset()` method sets CCMR2_Output to value 0"]
161impl crate::Resettable for Ccmr2OutputSpec {}
stm32l476/tim8/ccmr2_output.rs

stm32l476/tim8/
ccmr2_output.rs
