Struct stm32l4::stm32l4x1::can1::RegisterBlock

source · [−]
#[repr(C)]
pub struct RegisterBlock {
Show 15 fields
    pub mcr: Reg<MCR_SPEC>,
    pub msr: Reg<MSR_SPEC>,
    pub tsr: Reg<TSR_SPEC>,
    pub rfr: [Reg<RFR_SPEC>; 2],
    pub ier: Reg<IER_SPEC>,
    pub esr: Reg<ESR_SPEC>,
    pub btr: Reg<BTR_SPEC>,
    pub tx: [TX; 3],
    pub rx: [RX; 2],
    pub fmr: Reg<FMR_SPEC>,
    pub fm1r: Reg<FM1R_SPEC>,
    pub fs1r: Reg<FS1R_SPEC>,
    pub ffa1r: Reg<FFA1R_SPEC>,
    pub fa1r: Reg<FA1R_SPEC>,
    pub fb: [FB; 28],
    /* private fields */

}
Expand description

Register block

Fields

mcr: Reg<MCR_SPEC>

0x00 - master control register

msr: Reg<MSR_SPEC>

0x04 - master status register

tsr: Reg<TSR_SPEC>

0x08 - transmit status register

rfr: [Reg<RFR_SPEC>; 2]

0x0c..0x14 - receive FIFO %s register

ier: Reg<IER_SPEC>

0x14 - interrupt enable register

esr: Reg<ESR_SPEC>

0x18 - interrupt enable register

btr: Reg<BTR_SPEC>

0x1c - bit timing register

tx: [TX; 3]

0x180..0x1b0 - CAN Transmit cluster

rx: [RX; 2]

0x1b0..0x1d0 - CAN Receive cluster

fmr: Reg<FMR_SPEC>

0x200 - filter master register

fm1r: Reg<FM1R_SPEC>

0x204 - filter mode register

fs1r: Reg<FS1R_SPEC>

0x20c - filter scale register

ffa1r: Reg<FFA1R_SPEC>

0x214 - filter FIFO assignment register

fa1r: Reg<FA1R_SPEC>

0x21c - filter activation register

fb: [FB; 28]

0x240..0x320 - CAN Filter Bank cluster

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