stm32l4/stm32l4x1/quadspi/
cr.rs

1///Register `CR` reader
2pub type R = crate::R<CRrs>;
3///Register `CR` writer
4pub type W = crate::W<CRrs>;
5/**Enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum EN {
11    ///0: QUADSPI is disabled
12    Disabled = 0,
13    ///1: QUADSPI is enabled
14    Enabled = 1,
15}
16impl From<EN> for bool {
17    #[inline(always)]
18    fn from(variant: EN) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `EN` reader - Enable
23pub type EN_R = crate::BitReader<EN>;
24impl EN_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> EN {
28        match self.bits {
29            false => EN::Disabled,
30            true => EN::Enabled,
31        }
32    }
33    ///QUADSPI is disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == EN::Disabled
37    }
38    ///QUADSPI is enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == EN::Enabled
42    }
43}
44///Field `EN` writer - Enable
45pub type EN_W<'a, REG> = crate::BitWriter<'a, REG, EN>;
46impl<'a, REG> EN_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///QUADSPI is disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(EN::Disabled)
54    }
55    ///QUADSPI is enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(EN::Enabled)
59    }
60}
61/**Abort request
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum ABORT {
67    ///0: No abort requested
68    NoAbortRequested = 0,
69    ///1: Abort requested
70    AbortRequested = 1,
71}
72impl From<ABORT> for bool {
73    #[inline(always)]
74    fn from(variant: ABORT) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `ABORT` reader - Abort request
79pub type ABORT_R = crate::BitReader<ABORT>;
80impl ABORT_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> ABORT {
84        match self.bits {
85            false => ABORT::NoAbortRequested,
86            true => ABORT::AbortRequested,
87        }
88    }
89    ///No abort requested
90    #[inline(always)]
91    pub fn is_no_abort_requested(&self) -> bool {
92        *self == ABORT::NoAbortRequested
93    }
94    ///Abort requested
95    #[inline(always)]
96    pub fn is_abort_requested(&self) -> bool {
97        *self == ABORT::AbortRequested
98    }
99}
100///Field `ABORT` writer - Abort request
101pub type ABORT_W<'a, REG> = crate::BitWriter<'a, REG, ABORT>;
102impl<'a, REG> ABORT_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///No abort requested
107    #[inline(always)]
108    pub fn no_abort_requested(self) -> &'a mut crate::W<REG> {
109        self.variant(ABORT::NoAbortRequested)
110    }
111    ///Abort requested
112    #[inline(always)]
113    pub fn abort_requested(self) -> &'a mut crate::W<REG> {
114        self.variant(ABORT::AbortRequested)
115    }
116}
117/**DMA enable
118
119Value on reset: 0*/
120#[cfg_attr(feature = "defmt", derive(defmt::Format))]
121#[derive(Clone, Copy, Debug, PartialEq, Eq)]
122pub enum DMAEN {
123    ///0: DMA is disabled for indirect mode
124    Disabled = 0,
125    ///1: DMA is enabled for indirect mode
126    Enabled = 1,
127}
128impl From<DMAEN> for bool {
129    #[inline(always)]
130    fn from(variant: DMAEN) -> Self {
131        variant as u8 != 0
132    }
133}
134///Field `DMAEN` reader - DMA enable
135pub type DMAEN_R = crate::BitReader<DMAEN>;
136impl DMAEN_R {
137    ///Get enumerated values variant
138    #[inline(always)]
139    pub const fn variant(&self) -> DMAEN {
140        match self.bits {
141            false => DMAEN::Disabled,
142            true => DMAEN::Enabled,
143        }
144    }
145    ///DMA is disabled for indirect mode
146    #[inline(always)]
147    pub fn is_disabled(&self) -> bool {
148        *self == DMAEN::Disabled
149    }
150    ///DMA is enabled for indirect mode
151    #[inline(always)]
152    pub fn is_enabled(&self) -> bool {
153        *self == DMAEN::Enabled
154    }
155}
156///Field `DMAEN` writer - DMA enable
157pub type DMAEN_W<'a, REG> = crate::BitWriter<'a, REG, DMAEN>;
158impl<'a, REG> DMAEN_W<'a, REG>
159where
160    REG: crate::Writable + crate::RegisterSpec,
161{
162    ///DMA is disabled for indirect mode
163    #[inline(always)]
164    pub fn disabled(self) -> &'a mut crate::W<REG> {
165        self.variant(DMAEN::Disabled)
166    }
167    ///DMA is enabled for indirect mode
168    #[inline(always)]
169    pub fn enabled(self) -> &'a mut crate::W<REG> {
170        self.variant(DMAEN::Enabled)
171    }
172}
173/**Timeout counter enable
174
175Value on reset: 0*/
176#[cfg_attr(feature = "defmt", derive(defmt::Format))]
177#[derive(Clone, Copy, Debug, PartialEq, Eq)]
178pub enum TCEN {
179    ///0: Timeout counter is disabled, and thus the chip select (nCS) remains active indefinitely after an access in memory-mapped mode.
180    Disabled = 0,
181    ///1: Timeout counter is enabled, and thus the chip select is released in memory-mapped mode after TIMEOUT\[15:0\] cycles of Flash memory inactivity.
182    Enabled = 1,
183}
184impl From<TCEN> for bool {
185    #[inline(always)]
186    fn from(variant: TCEN) -> Self {
187        variant as u8 != 0
188    }
189}
190///Field `TCEN` reader - Timeout counter enable
191pub type TCEN_R = crate::BitReader<TCEN>;
192impl TCEN_R {
193    ///Get enumerated values variant
194    #[inline(always)]
195    pub const fn variant(&self) -> TCEN {
196        match self.bits {
197            false => TCEN::Disabled,
198            true => TCEN::Enabled,
199        }
200    }
201    ///Timeout counter is disabled, and thus the chip select (nCS) remains active indefinitely after an access in memory-mapped mode.
202    #[inline(always)]
203    pub fn is_disabled(&self) -> bool {
204        *self == TCEN::Disabled
205    }
206    ///Timeout counter is enabled, and thus the chip select is released in memory-mapped mode after TIMEOUT\[15:0\] cycles of Flash memory inactivity.
207    #[inline(always)]
208    pub fn is_enabled(&self) -> bool {
209        *self == TCEN::Enabled
210    }
211}
212///Field `TCEN` writer - Timeout counter enable
213pub type TCEN_W<'a, REG> = crate::BitWriter<'a, REG, TCEN>;
214impl<'a, REG> TCEN_W<'a, REG>
215where
216    REG: crate::Writable + crate::RegisterSpec,
217{
218    ///Timeout counter is disabled, and thus the chip select (nCS) remains active indefinitely after an access in memory-mapped mode.
219    #[inline(always)]
220    pub fn disabled(self) -> &'a mut crate::W<REG> {
221        self.variant(TCEN::Disabled)
222    }
223    ///Timeout counter is enabled, and thus the chip select is released in memory-mapped mode after TIMEOUT\[15:0\] cycles of Flash memory inactivity.
224    #[inline(always)]
225    pub fn enabled(self) -> &'a mut crate::W<REG> {
226        self.variant(TCEN::Enabled)
227    }
228}
229/**Sample shift
230
231Value on reset: 0*/
232#[cfg_attr(feature = "defmt", derive(defmt::Format))]
233#[derive(Clone, Copy, Debug, PartialEq, Eq)]
234pub enum SSHIFT {
235    ///0: No shift
236    NoShift = 0,
237    ///1: 1/2 cycle shift
238    OneHalfCycleShift = 1,
239}
240impl From<SSHIFT> for bool {
241    #[inline(always)]
242    fn from(variant: SSHIFT) -> Self {
243        variant as u8 != 0
244    }
245}
246///Field `SSHIFT` reader - Sample shift
247pub type SSHIFT_R = crate::BitReader<SSHIFT>;
248impl SSHIFT_R {
249    ///Get enumerated values variant
250    #[inline(always)]
251    pub const fn variant(&self) -> SSHIFT {
252        match self.bits {
253            false => SSHIFT::NoShift,
254            true => SSHIFT::OneHalfCycleShift,
255        }
256    }
257    ///No shift
258    #[inline(always)]
259    pub fn is_no_shift(&self) -> bool {
260        *self == SSHIFT::NoShift
261    }
262    ///1/2 cycle shift
263    #[inline(always)]
264    pub fn is_one_half_cycle_shift(&self) -> bool {
265        *self == SSHIFT::OneHalfCycleShift
266    }
267}
268///Field `SSHIFT` writer - Sample shift
269pub type SSHIFT_W<'a, REG> = crate::BitWriter<'a, REG, SSHIFT>;
270impl<'a, REG> SSHIFT_W<'a, REG>
271where
272    REG: crate::Writable + crate::RegisterSpec,
273{
274    ///No shift
275    #[inline(always)]
276    pub fn no_shift(self) -> &'a mut crate::W<REG> {
277        self.variant(SSHIFT::NoShift)
278    }
279    ///1/2 cycle shift
280    #[inline(always)]
281    pub fn one_half_cycle_shift(self) -> &'a mut crate::W<REG> {
282        self.variant(SSHIFT::OneHalfCycleShift)
283    }
284}
285/**Dual-flash mode
286
287Value on reset: 0*/
288#[cfg_attr(feature = "defmt", derive(defmt::Format))]
289#[derive(Clone, Copy, Debug, PartialEq, Eq)]
290pub enum DFM {
291    ///0: Dual-flash mode disabled
292    Disabled = 0,
293    ///1: Dual-flash mode enabled
294    Enabled = 1,
295}
296impl From<DFM> for bool {
297    #[inline(always)]
298    fn from(variant: DFM) -> Self {
299        variant as u8 != 0
300    }
301}
302///Field `DFM` reader - Dual-flash mode
303pub type DFM_R = crate::BitReader<DFM>;
304impl DFM_R {
305    ///Get enumerated values variant
306    #[inline(always)]
307    pub const fn variant(&self) -> DFM {
308        match self.bits {
309            false => DFM::Disabled,
310            true => DFM::Enabled,
311        }
312    }
313    ///Dual-flash mode disabled
314    #[inline(always)]
315    pub fn is_disabled(&self) -> bool {
316        *self == DFM::Disabled
317    }
318    ///Dual-flash mode enabled
319    #[inline(always)]
320    pub fn is_enabled(&self) -> bool {
321        *self == DFM::Enabled
322    }
323}
324///Field `DFM` writer - Dual-flash mode
325pub type DFM_W<'a, REG> = crate::BitWriter<'a, REG, DFM>;
326impl<'a, REG> DFM_W<'a, REG>
327where
328    REG: crate::Writable + crate::RegisterSpec,
329{
330    ///Dual-flash mode disabled
331    #[inline(always)]
332    pub fn disabled(self) -> &'a mut crate::W<REG> {
333        self.variant(DFM::Disabled)
334    }
335    ///Dual-flash mode enabled
336    #[inline(always)]
337    pub fn enabled(self) -> &'a mut crate::W<REG> {
338        self.variant(DFM::Enabled)
339    }
340}
341/**FLASH memory selection
342
343Value on reset: 0*/
344#[cfg_attr(feature = "defmt", derive(defmt::Format))]
345#[derive(Clone, Copy, Debug, PartialEq, Eq)]
346pub enum FSEL {
347    ///0: FLASH 1 selected
348    SelectFlash1 = 0,
349    ///1: FLASH 2 selected
350    SelectFlash2 = 1,
351}
352impl From<FSEL> for bool {
353    #[inline(always)]
354    fn from(variant: FSEL) -> Self {
355        variant as u8 != 0
356    }
357}
358///Field `FSEL` reader - FLASH memory selection
359pub type FSEL_R = crate::BitReader<FSEL>;
360impl FSEL_R {
361    ///Get enumerated values variant
362    #[inline(always)]
363    pub const fn variant(&self) -> FSEL {
364        match self.bits {
365            false => FSEL::SelectFlash1,
366            true => FSEL::SelectFlash2,
367        }
368    }
369    ///FLASH 1 selected
370    #[inline(always)]
371    pub fn is_select_flash1(&self) -> bool {
372        *self == FSEL::SelectFlash1
373    }
374    ///FLASH 2 selected
375    #[inline(always)]
376    pub fn is_select_flash2(&self) -> bool {
377        *self == FSEL::SelectFlash2
378    }
379}
380///Field `FSEL` writer - FLASH memory selection
381pub type FSEL_W<'a, REG> = crate::BitWriter<'a, REG, FSEL>;
382impl<'a, REG> FSEL_W<'a, REG>
383where
384    REG: crate::Writable + crate::RegisterSpec,
385{
386    ///FLASH 1 selected
387    #[inline(always)]
388    pub fn select_flash1(self) -> &'a mut crate::W<REG> {
389        self.variant(FSEL::SelectFlash1)
390    }
391    ///FLASH 2 selected
392    #[inline(always)]
393    pub fn select_flash2(self) -> &'a mut crate::W<REG> {
394        self.variant(FSEL::SelectFlash2)
395    }
396}
397///Field `FTHRES` reader - IFO threshold level
398pub type FTHRES_R = crate::FieldReader;
399///Field `FTHRES` writer - IFO threshold level
400pub type FTHRES_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
401/**Transfer error interrupt enable
402
403Value on reset: 0*/
404#[cfg_attr(feature = "defmt", derive(defmt::Format))]
405#[derive(Clone, Copy, Debug, PartialEq, Eq)]
406pub enum TEIE {
407    ///0: Interrupt disable
408    Disabled = 0,
409    ///1: Interrupt enabled
410    Enabled = 1,
411}
412impl From<TEIE> for bool {
413    #[inline(always)]
414    fn from(variant: TEIE) -> Self {
415        variant as u8 != 0
416    }
417}
418///Field `TEIE` reader - Transfer error interrupt enable
419pub type TEIE_R = crate::BitReader<TEIE>;
420impl TEIE_R {
421    ///Get enumerated values variant
422    #[inline(always)]
423    pub const fn variant(&self) -> TEIE {
424        match self.bits {
425            false => TEIE::Disabled,
426            true => TEIE::Enabled,
427        }
428    }
429    ///Interrupt disable
430    #[inline(always)]
431    pub fn is_disabled(&self) -> bool {
432        *self == TEIE::Disabled
433    }
434    ///Interrupt enabled
435    #[inline(always)]
436    pub fn is_enabled(&self) -> bool {
437        *self == TEIE::Enabled
438    }
439}
440///Field `TEIE` writer - Transfer error interrupt enable
441pub type TEIE_W<'a, REG> = crate::BitWriter<'a, REG, TEIE>;
442impl<'a, REG> TEIE_W<'a, REG>
443where
444    REG: crate::Writable + crate::RegisterSpec,
445{
446    ///Interrupt disable
447    #[inline(always)]
448    pub fn disabled(self) -> &'a mut crate::W<REG> {
449        self.variant(TEIE::Disabled)
450    }
451    ///Interrupt enabled
452    #[inline(always)]
453    pub fn enabled(self) -> &'a mut crate::W<REG> {
454        self.variant(TEIE::Enabled)
455    }
456}
457///Field `TCIE` reader - Transfer complete interrupt enable
458pub use TEIE_R as TCIE_R;
459///Field `FTIE` reader - FIFO threshold interrupt enable
460pub use TEIE_R as FTIE_R;
461///Field `SMIE` reader - Status match interrupt enable
462pub use TEIE_R as SMIE_R;
463///Field `TOIE` reader - TimeOut interrupt enable
464pub use TEIE_R as TOIE_R;
465///Field `TCIE` writer - Transfer complete interrupt enable
466pub use TEIE_W as TCIE_W;
467///Field `FTIE` writer - FIFO threshold interrupt enable
468pub use TEIE_W as FTIE_W;
469///Field `SMIE` writer - Status match interrupt enable
470pub use TEIE_W as SMIE_W;
471///Field `TOIE` writer - TimeOut interrupt enable
472pub use TEIE_W as TOIE_W;
473/**Automatic poll mode stop
474
475Value on reset: 0*/
476#[cfg_attr(feature = "defmt", derive(defmt::Format))]
477#[derive(Clone, Copy, Debug, PartialEq, Eq)]
478pub enum APMS {
479    ///0: Automatic polling mode is stopped only by abort or by disabling the QUADSPI.
480    NotStopOnMatch = 0,
481    ///1: Automatic polling mode stops as soon as there is a match.
482    StopOnMatch = 1,
483}
484impl From<APMS> for bool {
485    #[inline(always)]
486    fn from(variant: APMS) -> Self {
487        variant as u8 != 0
488    }
489}
490///Field `APMS` reader - Automatic poll mode stop
491pub type APMS_R = crate::BitReader<APMS>;
492impl APMS_R {
493    ///Get enumerated values variant
494    #[inline(always)]
495    pub const fn variant(&self) -> APMS {
496        match self.bits {
497            false => APMS::NotStopOnMatch,
498            true => APMS::StopOnMatch,
499        }
500    }
501    ///Automatic polling mode is stopped only by abort or by disabling the QUADSPI.
502    #[inline(always)]
503    pub fn is_not_stop_on_match(&self) -> bool {
504        *self == APMS::NotStopOnMatch
505    }
506    ///Automatic polling mode stops as soon as there is a match.
507    #[inline(always)]
508    pub fn is_stop_on_match(&self) -> bool {
509        *self == APMS::StopOnMatch
510    }
511}
512///Field `APMS` writer - Automatic poll mode stop
513pub type APMS_W<'a, REG> = crate::BitWriter<'a, REG, APMS>;
514impl<'a, REG> APMS_W<'a, REG>
515where
516    REG: crate::Writable + crate::RegisterSpec,
517{
518    ///Automatic polling mode is stopped only by abort or by disabling the QUADSPI.
519    #[inline(always)]
520    pub fn not_stop_on_match(self) -> &'a mut crate::W<REG> {
521        self.variant(APMS::NotStopOnMatch)
522    }
523    ///Automatic polling mode stops as soon as there is a match.
524    #[inline(always)]
525    pub fn stop_on_match(self) -> &'a mut crate::W<REG> {
526        self.variant(APMS::StopOnMatch)
527    }
528}
529/**Polling match mode
530
531Value on reset: 0*/
532#[cfg_attr(feature = "defmt", derive(defmt::Format))]
533#[derive(Clone, Copy, Debug, PartialEq, Eq)]
534pub enum PMM {
535    ///0: AND match mode. SMF is set if all the unmasked bits received from the Flash memory match the corresponding bits in the match register.
536    AndMatch = 0,
537    ///1: OR match mode. SMF is set if any one of the unmasked bits received from the Flash memory matches its corresponding bit in the match register.
538    OrMatch = 1,
539}
540impl From<PMM> for bool {
541    #[inline(always)]
542    fn from(variant: PMM) -> Self {
543        variant as u8 != 0
544    }
545}
546///Field `PMM` reader - Polling match mode
547pub type PMM_R = crate::BitReader<PMM>;
548impl PMM_R {
549    ///Get enumerated values variant
550    #[inline(always)]
551    pub const fn variant(&self) -> PMM {
552        match self.bits {
553            false => PMM::AndMatch,
554            true => PMM::OrMatch,
555        }
556    }
557    ///AND match mode. SMF is set if all the unmasked bits received from the Flash memory match the corresponding bits in the match register.
558    #[inline(always)]
559    pub fn is_and_match(&self) -> bool {
560        *self == PMM::AndMatch
561    }
562    ///OR match mode. SMF is set if any one of the unmasked bits received from the Flash memory matches its corresponding bit in the match register.
563    #[inline(always)]
564    pub fn is_or_match(&self) -> bool {
565        *self == PMM::OrMatch
566    }
567}
568///Field `PMM` writer - Polling match mode
569pub type PMM_W<'a, REG> = crate::BitWriter<'a, REG, PMM>;
570impl<'a, REG> PMM_W<'a, REG>
571where
572    REG: crate::Writable + crate::RegisterSpec,
573{
574    ///AND match mode. SMF is set if all the unmasked bits received from the Flash memory match the corresponding bits in the match register.
575    #[inline(always)]
576    pub fn and_match(self) -> &'a mut crate::W<REG> {
577        self.variant(PMM::AndMatch)
578    }
579    ///OR match mode. SMF is set if any one of the unmasked bits received from the Flash memory matches its corresponding bit in the match register.
580    #[inline(always)]
581    pub fn or_match(self) -> &'a mut crate::W<REG> {
582        self.variant(PMM::OrMatch)
583    }
584}
585///Field `PRESCALER` reader - Clock prescaler
586pub type PRESCALER_R = crate::FieldReader;
587///Field `PRESCALER` writer - Clock prescaler
588pub type PRESCALER_W<'a, REG> = crate::FieldWriter<'a, REG, 8, u8, crate::Safe>;
589impl R {
590    ///Bit 0 - Enable
591    #[inline(always)]
592    pub fn en(&self) -> EN_R {
593        EN_R::new((self.bits & 1) != 0)
594    }
595    ///Bit 1 - Abort request
596    #[inline(always)]
597    pub fn abort(&self) -> ABORT_R {
598        ABORT_R::new(((self.bits >> 1) & 1) != 0)
599    }
600    ///Bit 2 - DMA enable
601    #[inline(always)]
602    pub fn dmaen(&self) -> DMAEN_R {
603        DMAEN_R::new(((self.bits >> 2) & 1) != 0)
604    }
605    ///Bit 3 - Timeout counter enable
606    #[inline(always)]
607    pub fn tcen(&self) -> TCEN_R {
608        TCEN_R::new(((self.bits >> 3) & 1) != 0)
609    }
610    ///Bit 4 - Sample shift
611    #[inline(always)]
612    pub fn sshift(&self) -> SSHIFT_R {
613        SSHIFT_R::new(((self.bits >> 4) & 1) != 0)
614    }
615    ///Bit 6 - Dual-flash mode
616    #[inline(always)]
617    pub fn dfm(&self) -> DFM_R {
618        DFM_R::new(((self.bits >> 6) & 1) != 0)
619    }
620    ///Bit 7 - FLASH memory selection
621    #[inline(always)]
622    pub fn fsel(&self) -> FSEL_R {
623        FSEL_R::new(((self.bits >> 7) & 1) != 0)
624    }
625    ///Bits 8:12 - IFO threshold level
626    #[inline(always)]
627    pub fn fthres(&self) -> FTHRES_R {
628        FTHRES_R::new(((self.bits >> 8) & 0x1f) as u8)
629    }
630    ///Bit 16 - Transfer error interrupt enable
631    #[inline(always)]
632    pub fn teie(&self) -> TEIE_R {
633        TEIE_R::new(((self.bits >> 16) & 1) != 0)
634    }
635    ///Bit 17 - Transfer complete interrupt enable
636    #[inline(always)]
637    pub fn tcie(&self) -> TCIE_R {
638        TCIE_R::new(((self.bits >> 17) & 1) != 0)
639    }
640    ///Bit 18 - FIFO threshold interrupt enable
641    #[inline(always)]
642    pub fn ftie(&self) -> FTIE_R {
643        FTIE_R::new(((self.bits >> 18) & 1) != 0)
644    }
645    ///Bit 19 - Status match interrupt enable
646    #[inline(always)]
647    pub fn smie(&self) -> SMIE_R {
648        SMIE_R::new(((self.bits >> 19) & 1) != 0)
649    }
650    ///Bit 20 - TimeOut interrupt enable
651    #[inline(always)]
652    pub fn toie(&self) -> TOIE_R {
653        TOIE_R::new(((self.bits >> 20) & 1) != 0)
654    }
655    ///Bit 22 - Automatic poll mode stop
656    #[inline(always)]
657    pub fn apms(&self) -> APMS_R {
658        APMS_R::new(((self.bits >> 22) & 1) != 0)
659    }
660    ///Bit 23 - Polling match mode
661    #[inline(always)]
662    pub fn pmm(&self) -> PMM_R {
663        PMM_R::new(((self.bits >> 23) & 1) != 0)
664    }
665    ///Bits 24:31 - Clock prescaler
666    #[inline(always)]
667    pub fn prescaler(&self) -> PRESCALER_R {
668        PRESCALER_R::new(((self.bits >> 24) & 0xff) as u8)
669    }
670}
671impl core::fmt::Debug for R {
672    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
673        f.debug_struct("CR")
674            .field("prescaler", &self.prescaler())
675            .field("pmm", &self.pmm())
676            .field("apms", &self.apms())
677            .field("teie", &self.teie())
678            .field("toie", &self.toie())
679            .field("smie", &self.smie())
680            .field("ftie", &self.ftie())
681            .field("tcie", &self.tcie())
682            .field("fthres", &self.fthres())
683            .field("fsel", &self.fsel())
684            .field("dfm", &self.dfm())
685            .field("sshift", &self.sshift())
686            .field("tcen", &self.tcen())
687            .field("dmaen", &self.dmaen())
688            .field("abort", &self.abort())
689            .field("en", &self.en())
690            .finish()
691    }
692}
693impl W {
694    ///Bit 0 - Enable
695    #[inline(always)]
696    pub fn en(&mut self) -> EN_W<CRrs> {
697        EN_W::new(self, 0)
698    }
699    ///Bit 1 - Abort request
700    #[inline(always)]
701    pub fn abort(&mut self) -> ABORT_W<CRrs> {
702        ABORT_W::new(self, 1)
703    }
704    ///Bit 2 - DMA enable
705    #[inline(always)]
706    pub fn dmaen(&mut self) -> DMAEN_W<CRrs> {
707        DMAEN_W::new(self, 2)
708    }
709    ///Bit 3 - Timeout counter enable
710    #[inline(always)]
711    pub fn tcen(&mut self) -> TCEN_W<CRrs> {
712        TCEN_W::new(self, 3)
713    }
714    ///Bit 4 - Sample shift
715    #[inline(always)]
716    pub fn sshift(&mut self) -> SSHIFT_W<CRrs> {
717        SSHIFT_W::new(self, 4)
718    }
719    ///Bit 6 - Dual-flash mode
720    #[inline(always)]
721    pub fn dfm(&mut self) -> DFM_W<CRrs> {
722        DFM_W::new(self, 6)
723    }
724    ///Bit 7 - FLASH memory selection
725    #[inline(always)]
726    pub fn fsel(&mut self) -> FSEL_W<CRrs> {
727        FSEL_W::new(self, 7)
728    }
729    ///Bits 8:12 - IFO threshold level
730    #[inline(always)]
731    pub fn fthres(&mut self) -> FTHRES_W<CRrs> {
732        FTHRES_W::new(self, 8)
733    }
734    ///Bit 16 - Transfer error interrupt enable
735    #[inline(always)]
736    pub fn teie(&mut self) -> TEIE_W<CRrs> {
737        TEIE_W::new(self, 16)
738    }
739    ///Bit 17 - Transfer complete interrupt enable
740    #[inline(always)]
741    pub fn tcie(&mut self) -> TCIE_W<CRrs> {
742        TCIE_W::new(self, 17)
743    }
744    ///Bit 18 - FIFO threshold interrupt enable
745    #[inline(always)]
746    pub fn ftie(&mut self) -> FTIE_W<CRrs> {
747        FTIE_W::new(self, 18)
748    }
749    ///Bit 19 - Status match interrupt enable
750    #[inline(always)]
751    pub fn smie(&mut self) -> SMIE_W<CRrs> {
752        SMIE_W::new(self, 19)
753    }
754    ///Bit 20 - TimeOut interrupt enable
755    #[inline(always)]
756    pub fn toie(&mut self) -> TOIE_W<CRrs> {
757        TOIE_W::new(self, 20)
758    }
759    ///Bit 22 - Automatic poll mode stop
760    #[inline(always)]
761    pub fn apms(&mut self) -> APMS_W<CRrs> {
762        APMS_W::new(self, 22)
763    }
764    ///Bit 23 - Polling match mode
765    #[inline(always)]
766    pub fn pmm(&mut self) -> PMM_W<CRrs> {
767        PMM_W::new(self, 23)
768    }
769    ///Bits 24:31 - Clock prescaler
770    #[inline(always)]
771    pub fn prescaler(&mut self) -> PRESCALER_W<CRrs> {
772        PRESCALER_W::new(self, 24)
773    }
774}
775/**control register
776
777You can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
778
779See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#QUADSPI:CR)*/
780pub struct CRrs;
781impl crate::RegisterSpec for CRrs {
782    type Ux = u32;
783}
784///`read()` method returns [`cr::R`](R) reader structure
785impl crate::Readable for CRrs {}
786///`write(|w| ..)` method takes [`cr::W`](W) writer structure
787impl crate::Writable for CRrs {
788    type Safety = crate::Unsafe;
789}
790///`reset()` method sets CR to value 0
791impl crate::Resettable for CRrs {}
stm32l4/stm32l4x1/quadspi/cr.rs

stm32l4/stm32l4x1/quadspi/
cr.rs
