stm32l4/stm32l4x1/adc1/
cr.rs

1///Register `CR` reader
2pub type R = crate::R<CRrs>;
3///Register `CR` writer
4pub type W = crate::W<CRrs>;
5/**ADEN
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum ADENR {
11    ///0: ADC disabled
12    Disabled = 0,
13    ///1: ADC enabled
14    Enabled = 1,
15}
16impl From<ADENR> for bool {
17    #[inline(always)]
18    fn from(variant: ADENR) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `ADEN` reader - ADEN
23pub type ADEN_R = crate::BitReader<ADENR>;
24impl ADEN_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> ADENR {
28        match self.bits {
29            false => ADENR::Disabled,
30            true => ADENR::Enabled,
31        }
32    }
33    ///ADC disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == ADENR::Disabled
37    }
38    ///ADC enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == ADENR::Enabled
42    }
43}
44/**ADEN
45
46Value on reset: 0*/
47#[cfg_attr(feature = "defmt", derive(defmt::Format))]
48#[derive(Clone, Copy, Debug, PartialEq, Eq)]
49pub enum ADENW {
50    ///1: Enable the ADC
51    Enabled = 1,
52}
53impl From<ADENW> for bool {
54    #[inline(always)]
55    fn from(variant: ADENW) -> Self {
56        variant as u8 != 0
57    }
58}
59///Field `ADEN` writer - ADEN
60pub type ADEN_W<'a, REG> = crate::BitWriter1S<'a, REG, ADENW>;
61impl<'a, REG> ADEN_W<'a, REG>
62where
63    REG: crate::Writable + crate::RegisterSpec,
64{
65    ///Enable the ADC
66    #[inline(always)]
67    pub fn enabled(self) -> &'a mut crate::W<REG> {
68        self.variant(ADENW::Enabled)
69    }
70}
71/**ADDIS
72
73Value on reset: 0*/
74#[cfg_attr(feature = "defmt", derive(defmt::Format))]
75#[derive(Clone, Copy, Debug, PartialEq, Eq)]
76pub enum ADDISR {
77    ///0: No disable command active
78    NotDisabling = 0,
79    ///1: ADC disabling
80    Disabling = 1,
81}
82impl From<ADDISR> for bool {
83    #[inline(always)]
84    fn from(variant: ADDISR) -> Self {
85        variant as u8 != 0
86    }
87}
88///Field `ADDIS` reader - ADDIS
89pub type ADDIS_R = crate::BitReader<ADDISR>;
90impl ADDIS_R {
91    ///Get enumerated values variant
92    #[inline(always)]
93    pub const fn variant(&self) -> ADDISR {
94        match self.bits {
95            false => ADDISR::NotDisabling,
96            true => ADDISR::Disabling,
97        }
98    }
99    ///No disable command active
100    #[inline(always)]
101    pub fn is_not_disabling(&self) -> bool {
102        *self == ADDISR::NotDisabling
103    }
104    ///ADC disabling
105    #[inline(always)]
106    pub fn is_disabling(&self) -> bool {
107        *self == ADDISR::Disabling
108    }
109}
110/**ADDIS
111
112Value on reset: 0*/
113#[cfg_attr(feature = "defmt", derive(defmt::Format))]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115pub enum ADDISW {
116    ///1: Disable the ADC
117    Disable = 1,
118}
119impl From<ADDISW> for bool {
120    #[inline(always)]
121    fn from(variant: ADDISW) -> Self {
122        variant as u8 != 0
123    }
124}
125///Field `ADDIS` writer - ADDIS
126pub type ADDIS_W<'a, REG> = crate::BitWriter1S<'a, REG, ADDISW>;
127impl<'a, REG> ADDIS_W<'a, REG>
128where
129    REG: crate::Writable + crate::RegisterSpec,
130{
131    ///Disable the ADC
132    #[inline(always)]
133    pub fn disable(self) -> &'a mut crate::W<REG> {
134        self.variant(ADDISW::Disable)
135    }
136}
137/**ADSTART
138
139Value on reset: 0*/
140#[cfg_attr(feature = "defmt", derive(defmt::Format))]
141#[derive(Clone, Copy, Debug, PartialEq, Eq)]
142pub enum ADSTARTR {
143    ///0: No conversion ongoing
144    NotActive = 0,
145    ///1: ADC operating and may be converting
146    Active = 1,
147}
148impl From<ADSTARTR> for bool {
149    #[inline(always)]
150    fn from(variant: ADSTARTR) -> Self {
151        variant as u8 != 0
152    }
153}
154///Field `ADSTART` reader - ADSTART
155pub type ADSTART_R = crate::BitReader<ADSTARTR>;
156impl ADSTART_R {
157    ///Get enumerated values variant
158    #[inline(always)]
159    pub const fn variant(&self) -> ADSTARTR {
160        match self.bits {
161            false => ADSTARTR::NotActive,
162            true => ADSTARTR::Active,
163        }
164    }
165    ///No conversion ongoing
166    #[inline(always)]
167    pub fn is_not_active(&self) -> bool {
168        *self == ADSTARTR::NotActive
169    }
170    ///ADC operating and may be converting
171    #[inline(always)]
172    pub fn is_active(&self) -> bool {
173        *self == ADSTARTR::Active
174    }
175}
176/**ADSTART
177
178Value on reset: 0*/
179#[cfg_attr(feature = "defmt", derive(defmt::Format))]
180#[derive(Clone, Copy, Debug, PartialEq, Eq)]
181pub enum ADSTARTW {
182    ///1: Start the ADC conversion (may be delayed for hardware triggers)
183    StartConversion = 1,
184}
185impl From<ADSTARTW> for bool {
186    #[inline(always)]
187    fn from(variant: ADSTARTW) -> Self {
188        variant as u8 != 0
189    }
190}
191///Field `ADSTART` writer - ADSTART
192pub type ADSTART_W<'a, REG> = crate::BitWriter1S<'a, REG, ADSTARTW>;
193impl<'a, REG> ADSTART_W<'a, REG>
194where
195    REG: crate::Writable + crate::RegisterSpec,
196{
197    ///Start the ADC conversion (may be delayed for hardware triggers)
198    #[inline(always)]
199    pub fn start_conversion(self) -> &'a mut crate::W<REG> {
200        self.variant(ADSTARTW::StartConversion)
201    }
202}
203///Field `JADSTART` reader - JADSTART
204pub use ADSTART_R as JADSTART_R;
205///Field `JADSTART` writer - JADSTART
206pub use ADSTART_W as JADSTART_W;
207/**ADSTP
208
209Value on reset: 0*/
210#[cfg_attr(feature = "defmt", derive(defmt::Format))]
211#[derive(Clone, Copy, Debug, PartialEq, Eq)]
212pub enum ADSTPR {
213    ///0: No stop command active
214    NotStopping = 0,
215    ///1: ADC stopping conversion
216    Stopping = 1,
217}
218impl From<ADSTPR> for bool {
219    #[inline(always)]
220    fn from(variant: ADSTPR) -> Self {
221        variant as u8 != 0
222    }
223}
224///Field `ADSTP` reader - ADSTP
225pub type ADSTP_R = crate::BitReader<ADSTPR>;
226impl ADSTP_R {
227    ///Get enumerated values variant
228    #[inline(always)]
229    pub const fn variant(&self) -> ADSTPR {
230        match self.bits {
231            false => ADSTPR::NotStopping,
232            true => ADSTPR::Stopping,
233        }
234    }
235    ///No stop command active
236    #[inline(always)]
237    pub fn is_not_stopping(&self) -> bool {
238        *self == ADSTPR::NotStopping
239    }
240    ///ADC stopping conversion
241    #[inline(always)]
242    pub fn is_stopping(&self) -> bool {
243        *self == ADSTPR::Stopping
244    }
245}
246/**ADSTP
247
248Value on reset: 0*/
249#[cfg_attr(feature = "defmt", derive(defmt::Format))]
250#[derive(Clone, Copy, Debug, PartialEq, Eq)]
251pub enum ADSTPW {
252    ///1: Stop the active conversion
253    StopConversion = 1,
254}
255impl From<ADSTPW> for bool {
256    #[inline(always)]
257    fn from(variant: ADSTPW) -> Self {
258        variant as u8 != 0
259    }
260}
261///Field `ADSTP` writer - ADSTP
262pub type ADSTP_W<'a, REG> = crate::BitWriter1S<'a, REG, ADSTPW>;
263impl<'a, REG> ADSTP_W<'a, REG>
264where
265    REG: crate::Writable + crate::RegisterSpec,
266{
267    ///Stop the active conversion
268    #[inline(always)]
269    pub fn stop_conversion(self) -> &'a mut crate::W<REG> {
270        self.variant(ADSTPW::StopConversion)
271    }
272}
273///Field `JADSTP` reader - JADSTP
274pub use ADSTP_R as JADSTP_R;
275///Field `JADSTP` writer - JADSTP
276pub use ADSTP_W as JADSTP_W;
277/**ADVREGEN
278
279Value on reset: 0*/
280#[cfg_attr(feature = "defmt", derive(defmt::Format))]
281#[derive(Clone, Copy, Debug, PartialEq, Eq)]
282pub enum ADVREGEN {
283    ///0: ADC Voltage regulator disabled
284    Disabled = 0,
285    ///1: ADC Voltage regulator enabled
286    Enabled = 1,
287}
288impl From<ADVREGEN> for bool {
289    #[inline(always)]
290    fn from(variant: ADVREGEN) -> Self {
291        variant as u8 != 0
292    }
293}
294///Field `ADVREGEN` reader - ADVREGEN
295pub type ADVREGEN_R = crate::BitReader<ADVREGEN>;
296impl ADVREGEN_R {
297    ///Get enumerated values variant
298    #[inline(always)]
299    pub const fn variant(&self) -> ADVREGEN {
300        match self.bits {
301            false => ADVREGEN::Disabled,
302            true => ADVREGEN::Enabled,
303        }
304    }
305    ///ADC Voltage regulator disabled
306    #[inline(always)]
307    pub fn is_disabled(&self) -> bool {
308        *self == ADVREGEN::Disabled
309    }
310    ///ADC Voltage regulator enabled
311    #[inline(always)]
312    pub fn is_enabled(&self) -> bool {
313        *self == ADVREGEN::Enabled
314    }
315}
316///Field `ADVREGEN` writer - ADVREGEN
317pub type ADVREGEN_W<'a, REG> = crate::BitWriter<'a, REG, ADVREGEN>;
318impl<'a, REG> ADVREGEN_W<'a, REG>
319where
320    REG: crate::Writable + crate::RegisterSpec,
321{
322    ///ADC Voltage regulator disabled
323    #[inline(always)]
324    pub fn disabled(self) -> &'a mut crate::W<REG> {
325        self.variant(ADVREGEN::Disabled)
326    }
327    ///ADC Voltage regulator enabled
328    #[inline(always)]
329    pub fn enabled(self) -> &'a mut crate::W<REG> {
330        self.variant(ADVREGEN::Enabled)
331    }
332}
333/**DEEPPWD
334
335Value on reset: 0*/
336#[cfg_attr(feature = "defmt", derive(defmt::Format))]
337#[derive(Clone, Copy, Debug, PartialEq, Eq)]
338pub enum DEEPPWD {
339    ///0: ADC not in Deep-power down
340    NotDeepPowerDown = 0,
341    ///1: ADC in Deep-power-down (default reset state)
342    DeepPowerDown = 1,
343}
344impl From<DEEPPWD> for bool {
345    #[inline(always)]
346    fn from(variant: DEEPPWD) -> Self {
347        variant as u8 != 0
348    }
349}
350///Field `DEEPPWD` reader - DEEPPWD
351pub type DEEPPWD_R = crate::BitReader<DEEPPWD>;
352impl DEEPPWD_R {
353    ///Get enumerated values variant
354    #[inline(always)]
355    pub const fn variant(&self) -> DEEPPWD {
356        match self.bits {
357            false => DEEPPWD::NotDeepPowerDown,
358            true => DEEPPWD::DeepPowerDown,
359        }
360    }
361    ///ADC not in Deep-power down
362    #[inline(always)]
363    pub fn is_not_deep_power_down(&self) -> bool {
364        *self == DEEPPWD::NotDeepPowerDown
365    }
366    ///ADC in Deep-power-down (default reset state)
367    #[inline(always)]
368    pub fn is_deep_power_down(&self) -> bool {
369        *self == DEEPPWD::DeepPowerDown
370    }
371}
372///Field `DEEPPWD` writer - DEEPPWD
373pub type DEEPPWD_W<'a, REG> = crate::BitWriter<'a, REG, DEEPPWD>;
374impl<'a, REG> DEEPPWD_W<'a, REG>
375where
376    REG: crate::Writable + crate::RegisterSpec,
377{
378    ///ADC not in Deep-power down
379    #[inline(always)]
380    pub fn not_deep_power_down(self) -> &'a mut crate::W<REG> {
381        self.variant(DEEPPWD::NotDeepPowerDown)
382    }
383    ///ADC in Deep-power-down (default reset state)
384    #[inline(always)]
385    pub fn deep_power_down(self) -> &'a mut crate::W<REG> {
386        self.variant(DEEPPWD::DeepPowerDown)
387    }
388}
389/**ADCALDIF
390
391Value on reset: 0*/
392#[cfg_attr(feature = "defmt", derive(defmt::Format))]
393#[derive(Clone, Copy, Debug, PartialEq, Eq)]
394pub enum ADCALDIF {
395    ///0: Calibration for single-ended mode
396    SingleEnded = 0,
397    ///1: Calibration for differential mode
398    Differential = 1,
399}
400impl From<ADCALDIF> for bool {
401    #[inline(always)]
402    fn from(variant: ADCALDIF) -> Self {
403        variant as u8 != 0
404    }
405}
406///Field `ADCALDIF` reader - ADCALDIF
407pub type ADCALDIF_R = crate::BitReader<ADCALDIF>;
408impl ADCALDIF_R {
409    ///Get enumerated values variant
410    #[inline(always)]
411    pub const fn variant(&self) -> ADCALDIF {
412        match self.bits {
413            false => ADCALDIF::SingleEnded,
414            true => ADCALDIF::Differential,
415        }
416    }
417    ///Calibration for single-ended mode
418    #[inline(always)]
419    pub fn is_single_ended(&self) -> bool {
420        *self == ADCALDIF::SingleEnded
421    }
422    ///Calibration for differential mode
423    #[inline(always)]
424    pub fn is_differential(&self) -> bool {
425        *self == ADCALDIF::Differential
426    }
427}
428///Field `ADCALDIF` writer - ADCALDIF
429pub type ADCALDIF_W<'a, REG> = crate::BitWriter<'a, REG, ADCALDIF>;
430impl<'a, REG> ADCALDIF_W<'a, REG>
431where
432    REG: crate::Writable + crate::RegisterSpec,
433{
434    ///Calibration for single-ended mode
435    #[inline(always)]
436    pub fn single_ended(self) -> &'a mut crate::W<REG> {
437        self.variant(ADCALDIF::SingleEnded)
438    }
439    ///Calibration for differential mode
440    #[inline(always)]
441    pub fn differential(self) -> &'a mut crate::W<REG> {
442        self.variant(ADCALDIF::Differential)
443    }
444}
445/**ADCAL
446
447Value on reset: 0*/
448#[cfg_attr(feature = "defmt", derive(defmt::Format))]
449#[derive(Clone, Copy, Debug, PartialEq, Eq)]
450pub enum ADCALR {
451    ///0: ADC calibration either not yet performed or completed
452    NotCalibrating = 0,
453    ///1: ADC calibration in progress
454    Calibrating = 1,
455}
456impl From<ADCALR> for bool {
457    #[inline(always)]
458    fn from(variant: ADCALR) -> Self {
459        variant as u8 != 0
460    }
461}
462///Field `ADCAL` reader - ADCAL
463pub type ADCAL_R = crate::BitReader<ADCALR>;
464impl ADCAL_R {
465    ///Get enumerated values variant
466    #[inline(always)]
467    pub const fn variant(&self) -> ADCALR {
468        match self.bits {
469            false => ADCALR::NotCalibrating,
470            true => ADCALR::Calibrating,
471        }
472    }
473    ///ADC calibration either not yet performed or completed
474    #[inline(always)]
475    pub fn is_not_calibrating(&self) -> bool {
476        *self == ADCALR::NotCalibrating
477    }
478    ///ADC calibration in progress
479    #[inline(always)]
480    pub fn is_calibrating(&self) -> bool {
481        *self == ADCALR::Calibrating
482    }
483}
484/**ADCAL
485
486Value on reset: 0*/
487#[cfg_attr(feature = "defmt", derive(defmt::Format))]
488#[derive(Clone, Copy, Debug, PartialEq, Eq)]
489pub enum ADCALW {
490    ///1: Start the ADC calibration sequence
491    StartCalibration = 1,
492}
493impl From<ADCALW> for bool {
494    #[inline(always)]
495    fn from(variant: ADCALW) -> Self {
496        variant as u8 != 0
497    }
498}
499///Field `ADCAL` writer - ADCAL
500pub type ADCAL_W<'a, REG> = crate::BitWriter1S<'a, REG, ADCALW>;
501impl<'a, REG> ADCAL_W<'a, REG>
502where
503    REG: crate::Writable + crate::RegisterSpec,
504{
505    ///Start the ADC calibration sequence
506    #[inline(always)]
507    pub fn start_calibration(self) -> &'a mut crate::W<REG> {
508        self.variant(ADCALW::StartCalibration)
509    }
510}
511impl R {
512    ///Bit 0 - ADEN
513    #[inline(always)]
514    pub fn aden(&self) -> ADEN_R {
515        ADEN_R::new((self.bits & 1) != 0)
516    }
517    ///Bit 1 - ADDIS
518    #[inline(always)]
519    pub fn addis(&self) -> ADDIS_R {
520        ADDIS_R::new(((self.bits >> 1) & 1) != 0)
521    }
522    ///Bit 2 - ADSTART
523    #[inline(always)]
524    pub fn adstart(&self) -> ADSTART_R {
525        ADSTART_R::new(((self.bits >> 2) & 1) != 0)
526    }
527    ///Bit 3 - JADSTART
528    #[inline(always)]
529    pub fn jadstart(&self) -> JADSTART_R {
530        JADSTART_R::new(((self.bits >> 3) & 1) != 0)
531    }
532    ///Bit 4 - ADSTP
533    #[inline(always)]
534    pub fn adstp(&self) -> ADSTP_R {
535        ADSTP_R::new(((self.bits >> 4) & 1) != 0)
536    }
537    ///Bit 5 - JADSTP
538    #[inline(always)]
539    pub fn jadstp(&self) -> JADSTP_R {
540        JADSTP_R::new(((self.bits >> 5) & 1) != 0)
541    }
542    ///Bit 28 - ADVREGEN
543    #[inline(always)]
544    pub fn advregen(&self) -> ADVREGEN_R {
545        ADVREGEN_R::new(((self.bits >> 28) & 1) != 0)
546    }
547    ///Bit 29 - DEEPPWD
548    #[inline(always)]
549    pub fn deeppwd(&self) -> DEEPPWD_R {
550        DEEPPWD_R::new(((self.bits >> 29) & 1) != 0)
551    }
552    ///Bit 30 - ADCALDIF
553    #[inline(always)]
554    pub fn adcaldif(&self) -> ADCALDIF_R {
555        ADCALDIF_R::new(((self.bits >> 30) & 1) != 0)
556    }
557    ///Bit 31 - ADCAL
558    #[inline(always)]
559    pub fn adcal(&self) -> ADCAL_R {
560        ADCAL_R::new(((self.bits >> 31) & 1) != 0)
561    }
562}
563impl core::fmt::Debug for R {
564    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
565        f.debug_struct("CR")
566            .field("adcal", &self.adcal())
567            .field("adcaldif", &self.adcaldif())
568            .field("deeppwd", &self.deeppwd())
569            .field("advregen", &self.advregen())
570            .field("adstp", &self.adstp())
571            .field("jadstp", &self.jadstp())
572            .field("adstart", &self.adstart())
573            .field("jadstart", &self.jadstart())
574            .field("addis", &self.addis())
575            .field("aden", &self.aden())
576            .finish()
577    }
578}
579impl W {
580    ///Bit 0 - ADEN
581    #[inline(always)]
582    pub fn aden(&mut self) -> ADEN_W<CRrs> {
583        ADEN_W::new(self, 0)
584    }
585    ///Bit 1 - ADDIS
586    #[inline(always)]
587    pub fn addis(&mut self) -> ADDIS_W<CRrs> {
588        ADDIS_W::new(self, 1)
589    }
590    ///Bit 2 - ADSTART
591    #[inline(always)]
592    pub fn adstart(&mut self) -> ADSTART_W<CRrs> {
593        ADSTART_W::new(self, 2)
594    }
595    ///Bit 3 - JADSTART
596    #[inline(always)]
597    pub fn jadstart(&mut self) -> JADSTART_W<CRrs> {
598        JADSTART_W::new(self, 3)
599    }
600    ///Bit 4 - ADSTP
601    #[inline(always)]
602    pub fn adstp(&mut self) -> ADSTP_W<CRrs> {
603        ADSTP_W::new(self, 4)
604    }
605    ///Bit 5 - JADSTP
606    #[inline(always)]
607    pub fn jadstp(&mut self) -> JADSTP_W<CRrs> {
608        JADSTP_W::new(self, 5)
609    }
610    ///Bit 28 - ADVREGEN
611    #[inline(always)]
612    pub fn advregen(&mut self) -> ADVREGEN_W<CRrs> {
613        ADVREGEN_W::new(self, 28)
614    }
615    ///Bit 29 - DEEPPWD
616    #[inline(always)]
617    pub fn deeppwd(&mut self) -> DEEPPWD_W<CRrs> {
618        DEEPPWD_W::new(self, 29)
619    }
620    ///Bit 30 - ADCALDIF
621    #[inline(always)]
622    pub fn adcaldif(&mut self) -> ADCALDIF_W<CRrs> {
623        ADCALDIF_W::new(self, 30)
624    }
625    ///Bit 31 - ADCAL
626    #[inline(always)]
627    pub fn adcal(&mut self) -> ADCAL_W<CRrs> {
628        ADCAL_W::new(self, 31)
629    }
630}
631/**control register
632
633You can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
634
635See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#ADC1:CR)*/
636pub struct CRrs;
637impl crate::RegisterSpec for CRrs {
638    type Ux = u32;
639}
640///`read()` method returns [`cr::R`](R) reader structure
641impl crate::Readable for CRrs {}
642///`write(|w| ..)` method takes [`cr::W`](W) writer structure
643impl crate::Writable for CRrs {
644    type Safety = crate::Unsafe;
645    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x8000_003f;
646}
647///`reset()` method sets CR to value 0
648impl crate::Resettable for CRrs {}
stm32l4/stm32l4x1/adc1/cr.rs

stm32l4/stm32l4x1/adc1/
cr.rs
