stm32l4/stm32l4x5/tim15/
dmar.rs

1///Register `DMAR` reader
2pub type R = crate::R<DMARrs>;
3///Register `DMAR` writer
4pub type W = crate::W<DMARrs>;
5///Field `DMAB` reader - DMA register for burst accesses
6pub type DMAB_R = crate::FieldReader<u16>;
7///Field `DMAB` writer - DMA register for burst accesses
8pub type DMAB_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
9impl R {
10    ///Bits 0:15 - DMA register for burst accesses
11    #[inline(always)]
12    pub fn dmab(&self) -> DMAB_R {
13        DMAB_R::new((self.bits & 0xffff) as u16)
14    }
15}
16impl core::fmt::Debug for R {
17    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
18        f.debug_struct("DMAR").field("dmab", &self.dmab()).finish()
19    }
20}
21impl W {
22    ///Bits 0:15 - DMA register for burst accesses
23    #[inline(always)]
24    pub fn dmab(&mut self) -> DMAB_W<DMARrs> {
25        DMAB_W::new(self, 0)
26    }
27}
28/**DMA address for full transfer
29
30You can [`read`](crate::Reg::read) this register and get [`dmar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
31
32See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x5.html#TIM15:DMAR)*/
33pub struct DMARrs;
34impl crate::RegisterSpec for DMARrs {
35    type Ux = u32;
36}
37///`read()` method returns [`dmar::R`](R) reader structure
38impl crate::Readable for DMARrs {}
39///`write(|w| ..)` method takes [`dmar::W`](W) writer structure
40impl crate::Writable for DMARrs {
41    type Safety = crate::Unsafe;
42}
43///`reset()` method sets DMAR to value 0
44impl crate::Resettable for DMARrs {}
stm32l4/stm32l4x5/tim15/dmar.rs

stm32l4/stm32l4x5/tim15/
dmar.rs
