stm32l4/stm32l4x5/sai1/ch/
cr2.rs

1///Register `CR2` reader
2pub type R = crate::R<CR2rs>;
3///Register `CR2` writer
4pub type W = crate::W<CR2rs>;
5/**FIFO threshold
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10#[repr(u8)]
11pub enum FTH {
12    ///0: FIFO empty
13    Empty = 0,
14    ///1: 1⁄4 FIFO
15    Quarter1 = 1,
16    ///2: 1⁄2 FIFO
17    Quarter2 = 2,
18    ///3: 3⁄4 FIFO
19    Quarter3 = 3,
20    ///4: FIFO full
21    Full = 4,
22}
23impl From<FTH> for u8 {
24    #[inline(always)]
25    fn from(variant: FTH) -> Self {
26        variant as _
27    }
28}
29impl crate::FieldSpec for FTH {
30    type Ux = u8;
31}
32impl crate::IsEnum for FTH {}
33///Field `FTH` reader - FIFO threshold
34pub type FTH_R = crate::FieldReader<FTH>;
35impl FTH_R {
36    ///Get enumerated values variant
37    #[inline(always)]
38    pub const fn variant(&self) -> Option<FTH> {
39        match self.bits {
40            0 => Some(FTH::Empty),
41            1 => Some(FTH::Quarter1),
42            2 => Some(FTH::Quarter2),
43            3 => Some(FTH::Quarter3),
44            4 => Some(FTH::Full),
45            _ => None,
46        }
47    }
48    ///FIFO empty
49    #[inline(always)]
50    pub fn is_empty(&self) -> bool {
51        *self == FTH::Empty
52    }
53    ///1⁄4 FIFO
54    #[inline(always)]
55    pub fn is_quarter1(&self) -> bool {
56        *self == FTH::Quarter1
57    }
58    ///1⁄2 FIFO
59    #[inline(always)]
60    pub fn is_quarter2(&self) -> bool {
61        *self == FTH::Quarter2
62    }
63    ///3⁄4 FIFO
64    #[inline(always)]
65    pub fn is_quarter3(&self) -> bool {
66        *self == FTH::Quarter3
67    }
68    ///FIFO full
69    #[inline(always)]
70    pub fn is_full(&self) -> bool {
71        *self == FTH::Full
72    }
73}
74///Field `FTH` writer - FIFO threshold
75pub type FTH_W<'a, REG> = crate::FieldWriter<'a, REG, 3, FTH>;
76impl<'a, REG> FTH_W<'a, REG>
77where
78    REG: crate::Writable + crate::RegisterSpec,
79    REG::Ux: From<u8>,
80{
81    ///FIFO empty
82    #[inline(always)]
83    pub fn empty(self) -> &'a mut crate::W<REG> {
84        self.variant(FTH::Empty)
85    }
86    ///1⁄4 FIFO
87    #[inline(always)]
88    pub fn quarter1(self) -> &'a mut crate::W<REG> {
89        self.variant(FTH::Quarter1)
90    }
91    ///1⁄2 FIFO
92    #[inline(always)]
93    pub fn quarter2(self) -> &'a mut crate::W<REG> {
94        self.variant(FTH::Quarter2)
95    }
96    ///3⁄4 FIFO
97    #[inline(always)]
98    pub fn quarter3(self) -> &'a mut crate::W<REG> {
99        self.variant(FTH::Quarter3)
100    }
101    ///FIFO full
102    #[inline(always)]
103    pub fn full(self) -> &'a mut crate::W<REG> {
104        self.variant(FTH::Full)
105    }
106}
107/**FIFO flush
108
109Value on reset: 0*/
110#[cfg_attr(feature = "defmt", derive(defmt::Format))]
111#[derive(Clone, Copy, Debug, PartialEq, Eq)]
112pub enum FFLUSH {
113    ///0: No FIFO flush
114    NoFlush = 0,
115    ///1: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared
116    Flush = 1,
117}
118impl From<FFLUSH> for bool {
119    #[inline(always)]
120    fn from(variant: FFLUSH) -> Self {
121        variant as u8 != 0
122    }
123}
124///Field `FFLUSH` writer - FIFO flush
125pub type FFLUSH_W<'a, REG> = crate::BitWriter<'a, REG, FFLUSH>;
126impl<'a, REG> FFLUSH_W<'a, REG>
127where
128    REG: crate::Writable + crate::RegisterSpec,
129{
130    ///No FIFO flush
131    #[inline(always)]
132    pub fn no_flush(self) -> &'a mut crate::W<REG> {
133        self.variant(FFLUSH::NoFlush)
134    }
135    ///FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared
136    #[inline(always)]
137    pub fn flush(self) -> &'a mut crate::W<REG> {
138        self.variant(FFLUSH::Flush)
139    }
140}
141///Field `TRIS` reader - Tristate management on data line
142pub type TRIS_R = crate::BitReader;
143///Field `TRIS` writer - Tristate management on data line
144pub type TRIS_W<'a, REG> = crate::BitWriter<'a, REG>;
145/**Mute
146
147Value on reset: 0*/
148#[cfg_attr(feature = "defmt", derive(defmt::Format))]
149#[derive(Clone, Copy, Debug, PartialEq, Eq)]
150pub enum MUTE {
151    ///0: No mute mode
152    Disabled = 0,
153    ///1: Mute mode enabled
154    Enabled = 1,
155}
156impl From<MUTE> for bool {
157    #[inline(always)]
158    fn from(variant: MUTE) -> Self {
159        variant as u8 != 0
160    }
161}
162///Field `MUTE` reader - Mute
163pub type MUTE_R = crate::BitReader<MUTE>;
164impl MUTE_R {
165    ///Get enumerated values variant
166    #[inline(always)]
167    pub const fn variant(&self) -> MUTE {
168        match self.bits {
169            false => MUTE::Disabled,
170            true => MUTE::Enabled,
171        }
172    }
173    ///No mute mode
174    #[inline(always)]
175    pub fn is_disabled(&self) -> bool {
176        *self == MUTE::Disabled
177    }
178    ///Mute mode enabled
179    #[inline(always)]
180    pub fn is_enabled(&self) -> bool {
181        *self == MUTE::Enabled
182    }
183}
184///Field `MUTE` writer - Mute
185pub type MUTE_W<'a, REG> = crate::BitWriter<'a, REG, MUTE>;
186impl<'a, REG> MUTE_W<'a, REG>
187where
188    REG: crate::Writable + crate::RegisterSpec,
189{
190    ///No mute mode
191    #[inline(always)]
192    pub fn disabled(self) -> &'a mut crate::W<REG> {
193        self.variant(MUTE::Disabled)
194    }
195    ///Mute mode enabled
196    #[inline(always)]
197    pub fn enabled(self) -> &'a mut crate::W<REG> {
198        self.variant(MUTE::Enabled)
199    }
200}
201/**Mute value
202
203Value on reset: 0*/
204#[cfg_attr(feature = "defmt", derive(defmt::Format))]
205#[derive(Clone, Copy, Debug, PartialEq, Eq)]
206pub enum MUTEVAL {
207    ///0: Bit value 0 is sent during the mute mode
208    SendZero = 0,
209    ///1: Last values are sent during the mute mode
210    SendLast = 1,
211}
212impl From<MUTEVAL> for bool {
213    #[inline(always)]
214    fn from(variant: MUTEVAL) -> Self {
215        variant as u8 != 0
216    }
217}
218///Field `MUTEVAL` reader - Mute value
219pub type MUTEVAL_R = crate::BitReader<MUTEVAL>;
220impl MUTEVAL_R {
221    ///Get enumerated values variant
222    #[inline(always)]
223    pub const fn variant(&self) -> MUTEVAL {
224        match self.bits {
225            false => MUTEVAL::SendZero,
226            true => MUTEVAL::SendLast,
227        }
228    }
229    ///Bit value 0 is sent during the mute mode
230    #[inline(always)]
231    pub fn is_send_zero(&self) -> bool {
232        *self == MUTEVAL::SendZero
233    }
234    ///Last values are sent during the mute mode
235    #[inline(always)]
236    pub fn is_send_last(&self) -> bool {
237        *self == MUTEVAL::SendLast
238    }
239}
240///Field `MUTEVAL` writer - Mute value
241pub type MUTEVAL_W<'a, REG> = crate::BitWriter<'a, REG, MUTEVAL>;
242impl<'a, REG> MUTEVAL_W<'a, REG>
243where
244    REG: crate::Writable + crate::RegisterSpec,
245{
246    ///Bit value 0 is sent during the mute mode
247    #[inline(always)]
248    pub fn send_zero(self) -> &'a mut crate::W<REG> {
249        self.variant(MUTEVAL::SendZero)
250    }
251    ///Last values are sent during the mute mode
252    #[inline(always)]
253    pub fn send_last(self) -> &'a mut crate::W<REG> {
254        self.variant(MUTEVAL::SendLast)
255    }
256}
257///Field `MUTECNT` reader - Mute counter
258pub type MUTECNT_R = crate::FieldReader;
259///Field `MUTECNT` writer - Mute counter
260pub type MUTECNT_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
261/**Complement bit
262
263Value on reset: 0*/
264#[cfg_attr(feature = "defmt", derive(defmt::Format))]
265#[derive(Clone, Copy, Debug, PartialEq, Eq)]
266pub enum CPL {
267    ///0: 1’s complement representation
268    OnesComplement = 0,
269    ///1: 2’s complement representation
270    TwosComplement = 1,
271}
272impl From<CPL> for bool {
273    #[inline(always)]
274    fn from(variant: CPL) -> Self {
275        variant as u8 != 0
276    }
277}
278///Field `CPL` reader - Complement bit
279pub type CPL_R = crate::BitReader<CPL>;
280impl CPL_R {
281    ///Get enumerated values variant
282    #[inline(always)]
283    pub const fn variant(&self) -> CPL {
284        match self.bits {
285            false => CPL::OnesComplement,
286            true => CPL::TwosComplement,
287        }
288    }
289    ///1’s complement representation
290    #[inline(always)]
291    pub fn is_ones_complement(&self) -> bool {
292        *self == CPL::OnesComplement
293    }
294    ///2’s complement representation
295    #[inline(always)]
296    pub fn is_twos_complement(&self) -> bool {
297        *self == CPL::TwosComplement
298    }
299}
300///Field `CPL` writer - Complement bit
301pub type CPL_W<'a, REG> = crate::BitWriter<'a, REG, CPL>;
302impl<'a, REG> CPL_W<'a, REG>
303where
304    REG: crate::Writable + crate::RegisterSpec,
305{
306    ///1’s complement representation
307    #[inline(always)]
308    pub fn ones_complement(self) -> &'a mut crate::W<REG> {
309        self.variant(CPL::OnesComplement)
310    }
311    ///2’s complement representation
312    #[inline(always)]
313    pub fn twos_complement(self) -> &'a mut crate::W<REG> {
314        self.variant(CPL::TwosComplement)
315    }
316}
317/**Companding mode
318
319Value on reset: 0*/
320#[cfg_attr(feature = "defmt", derive(defmt::Format))]
321#[derive(Clone, Copy, Debug, PartialEq, Eq)]
322#[repr(u8)]
323pub enum COMP {
324    ///0: No companding algorithm
325    NoCompanding = 0,
326    ///2: μ-Law algorithm
327    MuLaw = 2,
328    ///3: A-Law algorithm
329    Alaw = 3,
330}
331impl From<COMP> for u8 {
332    #[inline(always)]
333    fn from(variant: COMP) -> Self {
334        variant as _
335    }
336}
337impl crate::FieldSpec for COMP {
338    type Ux = u8;
339}
340impl crate::IsEnum for COMP {}
341///Field `COMP` reader - Companding mode
342pub type COMP_R = crate::FieldReader<COMP>;
343impl COMP_R {
344    ///Get enumerated values variant
345    #[inline(always)]
346    pub const fn variant(&self) -> Option<COMP> {
347        match self.bits {
348            0 => Some(COMP::NoCompanding),
349            2 => Some(COMP::MuLaw),
350            3 => Some(COMP::Alaw),
351            _ => None,
352        }
353    }
354    ///No companding algorithm
355    #[inline(always)]
356    pub fn is_no_companding(&self) -> bool {
357        *self == COMP::NoCompanding
358    }
359    ///μ-Law algorithm
360    #[inline(always)]
361    pub fn is_mu_law(&self) -> bool {
362        *self == COMP::MuLaw
363    }
364    ///A-Law algorithm
365    #[inline(always)]
366    pub fn is_alaw(&self) -> bool {
367        *self == COMP::Alaw
368    }
369}
370///Field `COMP` writer - Companding mode
371pub type COMP_W<'a, REG> = crate::FieldWriter<'a, REG, 2, COMP>;
372impl<'a, REG> COMP_W<'a, REG>
373where
374    REG: crate::Writable + crate::RegisterSpec,
375    REG::Ux: From<u8>,
376{
377    ///No companding algorithm
378    #[inline(always)]
379    pub fn no_companding(self) -> &'a mut crate::W<REG> {
380        self.variant(COMP::NoCompanding)
381    }
382    ///μ-Law algorithm
383    #[inline(always)]
384    pub fn mu_law(self) -> &'a mut crate::W<REG> {
385        self.variant(COMP::MuLaw)
386    }
387    ///A-Law algorithm
388    #[inline(always)]
389    pub fn alaw(self) -> &'a mut crate::W<REG> {
390        self.variant(COMP::Alaw)
391    }
392}
393impl R {
394    ///Bits 0:2 - FIFO threshold
395    #[inline(always)]
396    pub fn fth(&self) -> FTH_R {
397        FTH_R::new((self.bits & 7) as u8)
398    }
399    ///Bit 4 - Tristate management on data line
400    #[inline(always)]
401    pub fn tris(&self) -> TRIS_R {
402        TRIS_R::new(((self.bits >> 4) & 1) != 0)
403    }
404    ///Bit 5 - Mute
405    #[inline(always)]
406    pub fn mute(&self) -> MUTE_R {
407        MUTE_R::new(((self.bits >> 5) & 1) != 0)
408    }
409    ///Bit 6 - Mute value
410    #[inline(always)]
411    pub fn muteval(&self) -> MUTEVAL_R {
412        MUTEVAL_R::new(((self.bits >> 6) & 1) != 0)
413    }
414    ///Bits 7:12 - Mute counter
415    #[inline(always)]
416    pub fn mutecnt(&self) -> MUTECNT_R {
417        MUTECNT_R::new(((self.bits >> 7) & 0x3f) as u8)
418    }
419    ///Bit 13 - Complement bit
420    #[inline(always)]
421    pub fn cpl(&self) -> CPL_R {
422        CPL_R::new(((self.bits >> 13) & 1) != 0)
423    }
424    ///Bits 14:15 - Companding mode
425    #[inline(always)]
426    pub fn comp(&self) -> COMP_R {
427        COMP_R::new(((self.bits >> 14) & 3) as u8)
428    }
429}
430impl core::fmt::Debug for R {
431    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
432        f.debug_struct("CR2")
433            .field("comp", &self.comp())
434            .field("cpl", &self.cpl())
435            .field("mutecnt", &self.mutecnt())
436            .field("muteval", &self.muteval())
437            .field("mute", &self.mute())
438            .field("tris", &self.tris())
439            .field("fth", &self.fth())
440            .finish()
441    }
442}
443impl W {
444    ///Bits 0:2 - FIFO threshold
445    #[inline(always)]
446    pub fn fth(&mut self) -> FTH_W<CR2rs> {
447        FTH_W::new(self, 0)
448    }
449    ///Bit 3 - FIFO flush
450    #[inline(always)]
451    pub fn fflush(&mut self) -> FFLUSH_W<CR2rs> {
452        FFLUSH_W::new(self, 3)
453    }
454    ///Bit 4 - Tristate management on data line
455    #[inline(always)]
456    pub fn tris(&mut self) -> TRIS_W<CR2rs> {
457        TRIS_W::new(self, 4)
458    }
459    ///Bit 5 - Mute
460    #[inline(always)]
461    pub fn mute(&mut self) -> MUTE_W<CR2rs> {
462        MUTE_W::new(self, 5)
463    }
464    ///Bit 6 - Mute value
465    #[inline(always)]
466    pub fn muteval(&mut self) -> MUTEVAL_W<CR2rs> {
467        MUTEVAL_W::new(self, 6)
468    }
469    ///Bits 7:12 - Mute counter
470    #[inline(always)]
471    pub fn mutecnt(&mut self) -> MUTECNT_W<CR2rs> {
472        MUTECNT_W::new(self, 7)
473    }
474    ///Bit 13 - Complement bit
475    #[inline(always)]
476    pub fn cpl(&mut self) -> CPL_W<CR2rs> {
477        CPL_W::new(self, 13)
478    }
479    ///Bits 14:15 - Companding mode
480    #[inline(always)]
481    pub fn comp(&mut self) -> COMP_W<CR2rs> {
482        COMP_W::new(self, 14)
483    }
484}
485/**AConfiguration register 2
486
487You can [`read`](crate::Reg::read) this register and get [`cr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
488pub struct CR2rs;
489impl crate::RegisterSpec for CR2rs {
490    type Ux = u32;
491}
492///`read()` method returns [`cr2::R`](R) reader structure
493impl crate::Readable for CR2rs {}
494///`write(|w| ..)` method takes [`cr2::W`](W) writer structure
495impl crate::Writable for CR2rs {
496    type Safety = crate::Unsafe;
497}
498///`reset()` method sets CR2 to value 0
499impl crate::Resettable for CR2rs {}
stm32l4/stm32l4x5/sai1/ch/cr2.rs

stm32l4/stm32l4x5/sai1/ch/
cr2.rs
