stm32l4/stm32l4x5/rcc/
ccipr.rs

1///Register `CCIPR` reader
2pub type R = crate::R<CCIPRrs>;
3///Register `CCIPR` writer
4pub type W = crate::W<CCIPRrs>;
5/**USART1 clock source selection
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10#[repr(u8)]
11pub enum USART1SEL {
12    ///0: PCLK clock selected
13    Pclk = 0,
14    ///1: SYSCLK clock selected
15    Sysclk = 1,
16    ///2: HSI16 clock selected
17    Hsi16 = 2,
18    ///3: LSE clock selected
19    Lse = 3,
20}
21impl From<USART1SEL> for u8 {
22    #[inline(always)]
23    fn from(variant: USART1SEL) -> Self {
24        variant as _
25    }
26}
27impl crate::FieldSpec for USART1SEL {
28    type Ux = u8;
29}
30impl crate::IsEnum for USART1SEL {}
31///Field `USART1SEL` reader - USART1 clock source selection
32pub type USART1SEL_R = crate::FieldReader<USART1SEL>;
33impl USART1SEL_R {
34    ///Get enumerated values variant
35    #[inline(always)]
36    pub const fn variant(&self) -> USART1SEL {
37        match self.bits {
38            0 => USART1SEL::Pclk,
39            1 => USART1SEL::Sysclk,
40            2 => USART1SEL::Hsi16,
41            3 => USART1SEL::Lse,
42            _ => unreachable!(),
43        }
44    }
45    ///PCLK clock selected
46    #[inline(always)]
47    pub fn is_pclk(&self) -> bool {
48        *self == USART1SEL::Pclk
49    }
50    ///SYSCLK clock selected
51    #[inline(always)]
52    pub fn is_sysclk(&self) -> bool {
53        *self == USART1SEL::Sysclk
54    }
55    ///HSI16 clock selected
56    #[inline(always)]
57    pub fn is_hsi16(&self) -> bool {
58        *self == USART1SEL::Hsi16
59    }
60    ///LSE clock selected
61    #[inline(always)]
62    pub fn is_lse(&self) -> bool {
63        *self == USART1SEL::Lse
64    }
65}
66///Field `USART1SEL` writer - USART1 clock source selection
67pub type USART1SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2, USART1SEL, crate::Safe>;
68impl<'a, REG> USART1SEL_W<'a, REG>
69where
70    REG: crate::Writable + crate::RegisterSpec,
71    REG::Ux: From<u8>,
72{
73    ///PCLK clock selected
74    #[inline(always)]
75    pub fn pclk(self) -> &'a mut crate::W<REG> {
76        self.variant(USART1SEL::Pclk)
77    }
78    ///SYSCLK clock selected
79    #[inline(always)]
80    pub fn sysclk(self) -> &'a mut crate::W<REG> {
81        self.variant(USART1SEL::Sysclk)
82    }
83    ///HSI16 clock selected
84    #[inline(always)]
85    pub fn hsi16(self) -> &'a mut crate::W<REG> {
86        self.variant(USART1SEL::Hsi16)
87    }
88    ///LSE clock selected
89    #[inline(always)]
90    pub fn lse(self) -> &'a mut crate::W<REG> {
91        self.variant(USART1SEL::Lse)
92    }
93}
94///Field `USART2SEL` reader - USART2 clock source selection
95pub use USART1SEL_R as USART2SEL_R;
96///Field `USART3SEL` reader - USART3 clock source selection
97pub use USART1SEL_R as USART3SEL_R;
98///Field `USART2SEL` writer - USART2 clock source selection
99pub use USART1SEL_W as USART2SEL_W;
100///Field `USART3SEL` writer - USART3 clock source selection
101pub use USART1SEL_W as USART3SEL_W;
102///Field `UART4SEL` reader - UART4 clock source selection
103pub type UART4SEL_R = crate::FieldReader;
104///Field `UART4SEL` writer - UART4 clock source selection
105pub type UART4SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
106///Field `UART5SEL` reader - UART5 clock source selection
107pub type UART5SEL_R = crate::FieldReader;
108///Field `UART5SEL` writer - UART5 clock source selection
109pub type UART5SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
110/**LPUART1 clock source selection
111
112Value on reset: 0*/
113#[cfg_attr(feature = "defmt", derive(defmt::Format))]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115#[repr(u8)]
116pub enum LPUART1SEL {
117    ///0: PCLK clock selected
118    Pclk = 0,
119    ///1: SYSCLK clock selected
120    Sysclk = 1,
121    ///2: HSI16 clock selected
122    Hsi16 = 2,
123    ///3: LSE clock selected
124    Lse = 3,
125}
126impl From<LPUART1SEL> for u8 {
127    #[inline(always)]
128    fn from(variant: LPUART1SEL) -> Self {
129        variant as _
130    }
131}
132impl crate::FieldSpec for LPUART1SEL {
133    type Ux = u8;
134}
135impl crate::IsEnum for LPUART1SEL {}
136///Field `LPUART1SEL` reader - LPUART1 clock source selection
137pub type LPUART1SEL_R = crate::FieldReader<LPUART1SEL>;
138impl LPUART1SEL_R {
139    ///Get enumerated values variant
140    #[inline(always)]
141    pub const fn variant(&self) -> LPUART1SEL {
142        match self.bits {
143            0 => LPUART1SEL::Pclk,
144            1 => LPUART1SEL::Sysclk,
145            2 => LPUART1SEL::Hsi16,
146            3 => LPUART1SEL::Lse,
147            _ => unreachable!(),
148        }
149    }
150    ///PCLK clock selected
151    #[inline(always)]
152    pub fn is_pclk(&self) -> bool {
153        *self == LPUART1SEL::Pclk
154    }
155    ///SYSCLK clock selected
156    #[inline(always)]
157    pub fn is_sysclk(&self) -> bool {
158        *self == LPUART1SEL::Sysclk
159    }
160    ///HSI16 clock selected
161    #[inline(always)]
162    pub fn is_hsi16(&self) -> bool {
163        *self == LPUART1SEL::Hsi16
164    }
165    ///LSE clock selected
166    #[inline(always)]
167    pub fn is_lse(&self) -> bool {
168        *self == LPUART1SEL::Lse
169    }
170}
171///Field `LPUART1SEL` writer - LPUART1 clock source selection
172pub type LPUART1SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2, LPUART1SEL, crate::Safe>;
173impl<'a, REG> LPUART1SEL_W<'a, REG>
174where
175    REG: crate::Writable + crate::RegisterSpec,
176    REG::Ux: From<u8>,
177{
178    ///PCLK clock selected
179    #[inline(always)]
180    pub fn pclk(self) -> &'a mut crate::W<REG> {
181        self.variant(LPUART1SEL::Pclk)
182    }
183    ///SYSCLK clock selected
184    #[inline(always)]
185    pub fn sysclk(self) -> &'a mut crate::W<REG> {
186        self.variant(LPUART1SEL::Sysclk)
187    }
188    ///HSI16 clock selected
189    #[inline(always)]
190    pub fn hsi16(self) -> &'a mut crate::W<REG> {
191        self.variant(LPUART1SEL::Hsi16)
192    }
193    ///LSE clock selected
194    #[inline(always)]
195    pub fn lse(self) -> &'a mut crate::W<REG> {
196        self.variant(LPUART1SEL::Lse)
197    }
198}
199/**I2C1 clock source selection
200
201Value on reset: 0*/
202#[cfg_attr(feature = "defmt", derive(defmt::Format))]
203#[derive(Clone, Copy, Debug, PartialEq, Eq)]
204#[repr(u8)]
205pub enum I2C1SEL {
206    ///0: PCLK clock selected
207    Pclk = 0,
208    ///1: SYSCLK clock selected
209    Sysclk = 1,
210    ///2: HSI16 clock selected
211    Hsi16 = 2,
212}
213impl From<I2C1SEL> for u8 {
214    #[inline(always)]
215    fn from(variant: I2C1SEL) -> Self {
216        variant as _
217    }
218}
219impl crate::FieldSpec for I2C1SEL {
220    type Ux = u8;
221}
222impl crate::IsEnum for I2C1SEL {}
223///Field `I2C1SEL` reader - I2C1 clock source selection
224pub type I2C1SEL_R = crate::FieldReader<I2C1SEL>;
225impl I2C1SEL_R {
226    ///Get enumerated values variant
227    #[inline(always)]
228    pub const fn variant(&self) -> Option<I2C1SEL> {
229        match self.bits {
230            0 => Some(I2C1SEL::Pclk),
231            1 => Some(I2C1SEL::Sysclk),
232            2 => Some(I2C1SEL::Hsi16),
233            _ => None,
234        }
235    }
236    ///PCLK clock selected
237    #[inline(always)]
238    pub fn is_pclk(&self) -> bool {
239        *self == I2C1SEL::Pclk
240    }
241    ///SYSCLK clock selected
242    #[inline(always)]
243    pub fn is_sysclk(&self) -> bool {
244        *self == I2C1SEL::Sysclk
245    }
246    ///HSI16 clock selected
247    #[inline(always)]
248    pub fn is_hsi16(&self) -> bool {
249        *self == I2C1SEL::Hsi16
250    }
251}
252///Field `I2C1SEL` writer - I2C1 clock source selection
253pub type I2C1SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2, I2C1SEL>;
254impl<'a, REG> I2C1SEL_W<'a, REG>
255where
256    REG: crate::Writable + crate::RegisterSpec,
257    REG::Ux: From<u8>,
258{
259    ///PCLK clock selected
260    #[inline(always)]
261    pub fn pclk(self) -> &'a mut crate::W<REG> {
262        self.variant(I2C1SEL::Pclk)
263    }
264    ///SYSCLK clock selected
265    #[inline(always)]
266    pub fn sysclk(self) -> &'a mut crate::W<REG> {
267        self.variant(I2C1SEL::Sysclk)
268    }
269    ///HSI16 clock selected
270    #[inline(always)]
271    pub fn hsi16(self) -> &'a mut crate::W<REG> {
272        self.variant(I2C1SEL::Hsi16)
273    }
274}
275///Field `I2C2SEL` reader - I2C2 clock source selection
276pub use I2C1SEL_R as I2C2SEL_R;
277///Field `I2C3SEL` reader - I2C3 clock source selection
278pub use I2C1SEL_R as I2C3SEL_R;
279///Field `I2C2SEL` writer - I2C2 clock source selection
280pub use I2C1SEL_W as I2C2SEL_W;
281///Field `I2C3SEL` writer - I2C3 clock source selection
282pub use I2C1SEL_W as I2C3SEL_W;
283/**Low power timer 1 clock source selection
284
285Value on reset: 0*/
286#[cfg_attr(feature = "defmt", derive(defmt::Format))]
287#[derive(Clone, Copy, Debug, PartialEq, Eq)]
288#[repr(u8)]
289pub enum LPTIM1SEL {
290    ///0: PCLK clock selected
291    Pclk = 0,
292    ///1: LSI clock selected
293    Lsi = 1,
294    ///2: HSI16 clock selected
295    Hsi16 = 2,
296    ///3: LSE clock selected
297    Lse = 3,
298}
299impl From<LPTIM1SEL> for u8 {
300    #[inline(always)]
301    fn from(variant: LPTIM1SEL) -> Self {
302        variant as _
303    }
304}
305impl crate::FieldSpec for LPTIM1SEL {
306    type Ux = u8;
307}
308impl crate::IsEnum for LPTIM1SEL {}
309///Field `LPTIM1SEL` reader - Low power timer 1 clock source selection
310pub type LPTIM1SEL_R = crate::FieldReader<LPTIM1SEL>;
311impl LPTIM1SEL_R {
312    ///Get enumerated values variant
313    #[inline(always)]
314    pub const fn variant(&self) -> LPTIM1SEL {
315        match self.bits {
316            0 => LPTIM1SEL::Pclk,
317            1 => LPTIM1SEL::Lsi,
318            2 => LPTIM1SEL::Hsi16,
319            3 => LPTIM1SEL::Lse,
320            _ => unreachable!(),
321        }
322    }
323    ///PCLK clock selected
324    #[inline(always)]
325    pub fn is_pclk(&self) -> bool {
326        *self == LPTIM1SEL::Pclk
327    }
328    ///LSI clock selected
329    #[inline(always)]
330    pub fn is_lsi(&self) -> bool {
331        *self == LPTIM1SEL::Lsi
332    }
333    ///HSI16 clock selected
334    #[inline(always)]
335    pub fn is_hsi16(&self) -> bool {
336        *self == LPTIM1SEL::Hsi16
337    }
338    ///LSE clock selected
339    #[inline(always)]
340    pub fn is_lse(&self) -> bool {
341        *self == LPTIM1SEL::Lse
342    }
343}
344///Field `LPTIM1SEL` writer - Low power timer 1 clock source selection
345pub type LPTIM1SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2, LPTIM1SEL, crate::Safe>;
346impl<'a, REG> LPTIM1SEL_W<'a, REG>
347where
348    REG: crate::Writable + crate::RegisterSpec,
349    REG::Ux: From<u8>,
350{
351    ///PCLK clock selected
352    #[inline(always)]
353    pub fn pclk(self) -> &'a mut crate::W<REG> {
354        self.variant(LPTIM1SEL::Pclk)
355    }
356    ///LSI clock selected
357    #[inline(always)]
358    pub fn lsi(self) -> &'a mut crate::W<REG> {
359        self.variant(LPTIM1SEL::Lsi)
360    }
361    ///HSI16 clock selected
362    #[inline(always)]
363    pub fn hsi16(self) -> &'a mut crate::W<REG> {
364        self.variant(LPTIM1SEL::Hsi16)
365    }
366    ///LSE clock selected
367    #[inline(always)]
368    pub fn lse(self) -> &'a mut crate::W<REG> {
369        self.variant(LPTIM1SEL::Lse)
370    }
371}
372///Field `LPTIM2SEL` reader - Low power timer 2 clock source selection
373pub use LPTIM1SEL_R as LPTIM2SEL_R;
374///Field `LPTIM2SEL` writer - Low power timer 2 clock source selection
375pub use LPTIM1SEL_W as LPTIM2SEL_W;
376///Field `SAI1SEL` reader - SAI1 clock source selection
377pub type SAI1SEL_R = crate::FieldReader;
378///Field `SAI1SEL` writer - SAI1 clock source selection
379pub type SAI1SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
380///Field `SAI2SEL` reader - SAI2 clock source selection
381pub type SAI2SEL_R = crate::FieldReader;
382///Field `SAI2SEL` writer - SAI2 clock source selection
383pub type SAI2SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
384/**48 MHz clock source selection
385
386Value on reset: 0*/
387#[cfg_attr(feature = "defmt", derive(defmt::Format))]
388#[derive(Clone, Copy, Debug, PartialEq, Eq)]
389#[repr(u8)]
390pub enum CLK48SEL {
391    ///0: HSI48 clock selected (only for STM32L41x/L42x/L43x/L44x/L45x/L46x/L49x/L4Ax devices, otherwise no clock selected)
392    Hsi48 = 0,
393    ///1: PLLSAI1 clock selected
394    Pllsai1 = 1,
395    ///2: PLL clock selected
396    Pll = 2,
397    ///3: MSI clock selected
398    Msi = 3,
399}
400impl From<CLK48SEL> for u8 {
401    #[inline(always)]
402    fn from(variant: CLK48SEL) -> Self {
403        variant as _
404    }
405}
406impl crate::FieldSpec for CLK48SEL {
407    type Ux = u8;
408}
409impl crate::IsEnum for CLK48SEL {}
410///Field `CLK48SEL` reader - 48 MHz clock source selection
411pub type CLK48SEL_R = crate::FieldReader<CLK48SEL>;
412impl CLK48SEL_R {
413    ///Get enumerated values variant
414    #[inline(always)]
415    pub const fn variant(&self) -> CLK48SEL {
416        match self.bits {
417            0 => CLK48SEL::Hsi48,
418            1 => CLK48SEL::Pllsai1,
419            2 => CLK48SEL::Pll,
420            3 => CLK48SEL::Msi,
421            _ => unreachable!(),
422        }
423    }
424    ///HSI48 clock selected (only for STM32L41x/L42x/L43x/L44x/L45x/L46x/L49x/L4Ax devices, otherwise no clock selected)
425    #[inline(always)]
426    pub fn is_hsi48(&self) -> bool {
427        *self == CLK48SEL::Hsi48
428    }
429    ///PLLSAI1 clock selected
430    #[inline(always)]
431    pub fn is_pllsai1(&self) -> bool {
432        *self == CLK48SEL::Pllsai1
433    }
434    ///PLL clock selected
435    #[inline(always)]
436    pub fn is_pll(&self) -> bool {
437        *self == CLK48SEL::Pll
438    }
439    ///MSI clock selected
440    #[inline(always)]
441    pub fn is_msi(&self) -> bool {
442        *self == CLK48SEL::Msi
443    }
444}
445///Field `CLK48SEL` writer - 48 MHz clock source selection
446pub type CLK48SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2, CLK48SEL, crate::Safe>;
447impl<'a, REG> CLK48SEL_W<'a, REG>
448where
449    REG: crate::Writable + crate::RegisterSpec,
450    REG::Ux: From<u8>,
451{
452    ///HSI48 clock selected (only for STM32L41x/L42x/L43x/L44x/L45x/L46x/L49x/L4Ax devices, otherwise no clock selected)
453    #[inline(always)]
454    pub fn hsi48(self) -> &'a mut crate::W<REG> {
455        self.variant(CLK48SEL::Hsi48)
456    }
457    ///PLLSAI1 clock selected
458    #[inline(always)]
459    pub fn pllsai1(self) -> &'a mut crate::W<REG> {
460        self.variant(CLK48SEL::Pllsai1)
461    }
462    ///PLL clock selected
463    #[inline(always)]
464    pub fn pll(self) -> &'a mut crate::W<REG> {
465        self.variant(CLK48SEL::Pll)
466    }
467    ///MSI clock selected
468    #[inline(always)]
469    pub fn msi(self) -> &'a mut crate::W<REG> {
470        self.variant(CLK48SEL::Msi)
471    }
472}
473/**ADCs clock source selection
474
475Value on reset: 0*/
476#[cfg_attr(feature = "defmt", derive(defmt::Format))]
477#[derive(Clone, Copy, Debug, PartialEq, Eq)]
478#[repr(u8)]
479pub enum ADCSEL {
480    ///0: No clock selected
481    NoClock = 0,
482    ///1: PLLSAI1 clock selected
483    Pllsai1 = 1,
484    ///2: PLLSAI2 clock selected (only for STM32L47x/L48x/L49x/L4Ax devices)
485    Pllsai2 = 2,
486    ///3: SYSCLK clock selected
487    Sysclk = 3,
488}
489impl From<ADCSEL> for u8 {
490    #[inline(always)]
491    fn from(variant: ADCSEL) -> Self {
492        variant as _
493    }
494}
495impl crate::FieldSpec for ADCSEL {
496    type Ux = u8;
497}
498impl crate::IsEnum for ADCSEL {}
499///Field `ADCSEL` reader - ADCs clock source selection
500pub type ADCSEL_R = crate::FieldReader<ADCSEL>;
501impl ADCSEL_R {
502    ///Get enumerated values variant
503    #[inline(always)]
504    pub const fn variant(&self) -> ADCSEL {
505        match self.bits {
506            0 => ADCSEL::NoClock,
507            1 => ADCSEL::Pllsai1,
508            2 => ADCSEL::Pllsai2,
509            3 => ADCSEL::Sysclk,
510            _ => unreachable!(),
511        }
512    }
513    ///No clock selected
514    #[inline(always)]
515    pub fn is_no_clock(&self) -> bool {
516        *self == ADCSEL::NoClock
517    }
518    ///PLLSAI1 clock selected
519    #[inline(always)]
520    pub fn is_pllsai1(&self) -> bool {
521        *self == ADCSEL::Pllsai1
522    }
523    ///PLLSAI2 clock selected (only for STM32L47x/L48x/L49x/L4Ax devices)
524    #[inline(always)]
525    pub fn is_pllsai2(&self) -> bool {
526        *self == ADCSEL::Pllsai2
527    }
528    ///SYSCLK clock selected
529    #[inline(always)]
530    pub fn is_sysclk(&self) -> bool {
531        *self == ADCSEL::Sysclk
532    }
533}
534///Field `ADCSEL` writer - ADCs clock source selection
535pub type ADCSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2, ADCSEL, crate::Safe>;
536impl<'a, REG> ADCSEL_W<'a, REG>
537where
538    REG: crate::Writable + crate::RegisterSpec,
539    REG::Ux: From<u8>,
540{
541    ///No clock selected
542    #[inline(always)]
543    pub fn no_clock(self) -> &'a mut crate::W<REG> {
544        self.variant(ADCSEL::NoClock)
545    }
546    ///PLLSAI1 clock selected
547    #[inline(always)]
548    pub fn pllsai1(self) -> &'a mut crate::W<REG> {
549        self.variant(ADCSEL::Pllsai1)
550    }
551    ///PLLSAI2 clock selected (only for STM32L47x/L48x/L49x/L4Ax devices)
552    #[inline(always)]
553    pub fn pllsai2(self) -> &'a mut crate::W<REG> {
554        self.variant(ADCSEL::Pllsai2)
555    }
556    ///SYSCLK clock selected
557    #[inline(always)]
558    pub fn sysclk(self) -> &'a mut crate::W<REG> {
559        self.variant(ADCSEL::Sysclk)
560    }
561}
562///Field `SWPMI1SEL` reader - SWPMI1 clock source selection
563pub type SWPMI1SEL_R = crate::BitReader;
564///Field `SWPMI1SEL` writer - SWPMI1 clock source selection
565pub type SWPMI1SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
566///Field `DFSDMSEL` reader - DFSDM clock source selection
567pub type DFSDMSEL_R = crate::BitReader;
568///Field `DFSDMSEL` writer - DFSDM clock source selection
569pub type DFSDMSEL_W<'a, REG> = crate::BitWriter<'a, REG>;
570impl R {
571    ///Bits 0:1 - USART1 clock source selection
572    #[inline(always)]
573    pub fn usart1sel(&self) -> USART1SEL_R {
574        USART1SEL_R::new((self.bits & 3) as u8)
575    }
576    ///Bits 2:3 - USART2 clock source selection
577    #[inline(always)]
578    pub fn usart2sel(&self) -> USART2SEL_R {
579        USART2SEL_R::new(((self.bits >> 2) & 3) as u8)
580    }
581    ///Bits 4:5 - USART3 clock source selection
582    #[inline(always)]
583    pub fn usart3sel(&self) -> USART3SEL_R {
584        USART3SEL_R::new(((self.bits >> 4) & 3) as u8)
585    }
586    ///Bits 6:7 - UART4 clock source selection
587    #[inline(always)]
588    pub fn uart4sel(&self) -> UART4SEL_R {
589        UART4SEL_R::new(((self.bits >> 6) & 3) as u8)
590    }
591    ///Bits 8:9 - UART5 clock source selection
592    #[inline(always)]
593    pub fn uart5sel(&self) -> UART5SEL_R {
594        UART5SEL_R::new(((self.bits >> 8) & 3) as u8)
595    }
596    ///Bits 10:11 - LPUART1 clock source selection
597    #[inline(always)]
598    pub fn lpuart1sel(&self) -> LPUART1SEL_R {
599        LPUART1SEL_R::new(((self.bits >> 10) & 3) as u8)
600    }
601    ///Bits 12:13 - I2C1 clock source selection
602    #[inline(always)]
603    pub fn i2c1sel(&self) -> I2C1SEL_R {
604        I2C1SEL_R::new(((self.bits >> 12) & 3) as u8)
605    }
606    ///Bits 14:15 - I2C2 clock source selection
607    #[inline(always)]
608    pub fn i2c2sel(&self) -> I2C2SEL_R {
609        I2C2SEL_R::new(((self.bits >> 14) & 3) as u8)
610    }
611    ///Bits 16:17 - I2C3 clock source selection
612    #[inline(always)]
613    pub fn i2c3sel(&self) -> I2C3SEL_R {
614        I2C3SEL_R::new(((self.bits >> 16) & 3) as u8)
615    }
616    ///Bits 18:19 - Low power timer 1 clock source selection
617    #[inline(always)]
618    pub fn lptim1sel(&self) -> LPTIM1SEL_R {
619        LPTIM1SEL_R::new(((self.bits >> 18) & 3) as u8)
620    }
621    ///Bits 20:21 - Low power timer 2 clock source selection
622    #[inline(always)]
623    pub fn lptim2sel(&self) -> LPTIM2SEL_R {
624        LPTIM2SEL_R::new(((self.bits >> 20) & 3) as u8)
625    }
626    ///Bits 22:23 - SAI1 clock source selection
627    #[inline(always)]
628    pub fn sai1sel(&self) -> SAI1SEL_R {
629        SAI1SEL_R::new(((self.bits >> 22) & 3) as u8)
630    }
631    ///Bits 24:25 - SAI2 clock source selection
632    #[inline(always)]
633    pub fn sai2sel(&self) -> SAI2SEL_R {
634        SAI2SEL_R::new(((self.bits >> 24) & 3) as u8)
635    }
636    ///Bits 26:27 - 48 MHz clock source selection
637    #[inline(always)]
638    pub fn clk48sel(&self) -> CLK48SEL_R {
639        CLK48SEL_R::new(((self.bits >> 26) & 3) as u8)
640    }
641    ///Bits 28:29 - ADCs clock source selection
642    #[inline(always)]
643    pub fn adcsel(&self) -> ADCSEL_R {
644        ADCSEL_R::new(((self.bits >> 28) & 3) as u8)
645    }
646    ///Bit 30 - SWPMI1 clock source selection
647    #[inline(always)]
648    pub fn swpmi1sel(&self) -> SWPMI1SEL_R {
649        SWPMI1SEL_R::new(((self.bits >> 30) & 1) != 0)
650    }
651    ///Bit 31 - DFSDM clock source selection
652    #[inline(always)]
653    pub fn dfsdmsel(&self) -> DFSDMSEL_R {
654        DFSDMSEL_R::new(((self.bits >> 31) & 1) != 0)
655    }
656}
657impl core::fmt::Debug for R {
658    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
659        f.debug_struct("CCIPR")
660            .field("dfsdmsel", &self.dfsdmsel())
661            .field("swpmi1sel", &self.swpmi1sel())
662            .field("adcsel", &self.adcsel())
663            .field("clk48sel", &self.clk48sel())
664            .field("sai2sel", &self.sai2sel())
665            .field("sai1sel", &self.sai1sel())
666            .field("lptim1sel", &self.lptim1sel())
667            .field("lptim2sel", &self.lptim2sel())
668            .field("i2c1sel", &self.i2c1sel())
669            .field("i2c3sel", &self.i2c3sel())
670            .field("i2c2sel", &self.i2c2sel())
671            .field("lpuart1sel", &self.lpuart1sel())
672            .field("uart5sel", &self.uart5sel())
673            .field("uart4sel", &self.uart4sel())
674            .field("usart1sel", &self.usart1sel())
675            .field("usart3sel", &self.usart3sel())
676            .field("usart2sel", &self.usart2sel())
677            .finish()
678    }
679}
680impl W {
681    ///Bits 0:1 - USART1 clock source selection
682    #[inline(always)]
683    pub fn usart1sel(&mut self) -> USART1SEL_W<CCIPRrs> {
684        USART1SEL_W::new(self, 0)
685    }
686    ///Bits 2:3 - USART2 clock source selection
687    #[inline(always)]
688    pub fn usart2sel(&mut self) -> USART2SEL_W<CCIPRrs> {
689        USART2SEL_W::new(self, 2)
690    }
691    ///Bits 4:5 - USART3 clock source selection
692    #[inline(always)]
693    pub fn usart3sel(&mut self) -> USART3SEL_W<CCIPRrs> {
694        USART3SEL_W::new(self, 4)
695    }
696    ///Bits 6:7 - UART4 clock source selection
697    #[inline(always)]
698    pub fn uart4sel(&mut self) -> UART4SEL_W<CCIPRrs> {
699        UART4SEL_W::new(self, 6)
700    }
701    ///Bits 8:9 - UART5 clock source selection
702    #[inline(always)]
703    pub fn uart5sel(&mut self) -> UART5SEL_W<CCIPRrs> {
704        UART5SEL_W::new(self, 8)
705    }
706    ///Bits 10:11 - LPUART1 clock source selection
707    #[inline(always)]
708    pub fn lpuart1sel(&mut self) -> LPUART1SEL_W<CCIPRrs> {
709        LPUART1SEL_W::new(self, 10)
710    }
711    ///Bits 12:13 - I2C1 clock source selection
712    #[inline(always)]
713    pub fn i2c1sel(&mut self) -> I2C1SEL_W<CCIPRrs> {
714        I2C1SEL_W::new(self, 12)
715    }
716    ///Bits 14:15 - I2C2 clock source selection
717    #[inline(always)]
718    pub fn i2c2sel(&mut self) -> I2C2SEL_W<CCIPRrs> {
719        I2C2SEL_W::new(self, 14)
720    }
721    ///Bits 16:17 - I2C3 clock source selection
722    #[inline(always)]
723    pub fn i2c3sel(&mut self) -> I2C3SEL_W<CCIPRrs> {
724        I2C3SEL_W::new(self, 16)
725    }
726    ///Bits 18:19 - Low power timer 1 clock source selection
727    #[inline(always)]
728    pub fn lptim1sel(&mut self) -> LPTIM1SEL_W<CCIPRrs> {
729        LPTIM1SEL_W::new(self, 18)
730    }
731    ///Bits 20:21 - Low power timer 2 clock source selection
732    #[inline(always)]
733    pub fn lptim2sel(&mut self) -> LPTIM2SEL_W<CCIPRrs> {
734        LPTIM2SEL_W::new(self, 20)
735    }
736    ///Bits 22:23 - SAI1 clock source selection
737    #[inline(always)]
738    pub fn sai1sel(&mut self) -> SAI1SEL_W<CCIPRrs> {
739        SAI1SEL_W::new(self, 22)
740    }
741    ///Bits 24:25 - SAI2 clock source selection
742    #[inline(always)]
743    pub fn sai2sel(&mut self) -> SAI2SEL_W<CCIPRrs> {
744        SAI2SEL_W::new(self, 24)
745    }
746    ///Bits 26:27 - 48 MHz clock source selection
747    #[inline(always)]
748    pub fn clk48sel(&mut self) -> CLK48SEL_W<CCIPRrs> {
749        CLK48SEL_W::new(self, 26)
750    }
751    ///Bits 28:29 - ADCs clock source selection
752    #[inline(always)]
753    pub fn adcsel(&mut self) -> ADCSEL_W<CCIPRrs> {
754        ADCSEL_W::new(self, 28)
755    }
756    ///Bit 30 - SWPMI1 clock source selection
757    #[inline(always)]
758    pub fn swpmi1sel(&mut self) -> SWPMI1SEL_W<CCIPRrs> {
759        SWPMI1SEL_W::new(self, 30)
760    }
761    ///Bit 31 - DFSDM clock source selection
762    #[inline(always)]
763    pub fn dfsdmsel(&mut self) -> DFSDMSEL_W<CCIPRrs> {
764        DFSDMSEL_W::new(self, 31)
765    }
766}
767/**CCIPR
768
769You can [`read`](crate::Reg::read) this register and get [`ccipr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccipr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
770
771See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x5.html#RCC:CCIPR)*/
772pub struct CCIPRrs;
773impl crate::RegisterSpec for CCIPRrs {
774    type Ux = u32;
775}
776///`read()` method returns [`ccipr::R`](R) reader structure
777impl crate::Readable for CCIPRrs {}
778///`write(|w| ..)` method takes [`ccipr::W`](W) writer structure
779impl crate::Writable for CCIPRrs {
780    type Safety = crate::Unsafe;
781}
782///`reset()` method sets CCIPR to value 0
783impl crate::Resettable for CCIPRrs {}
stm32l4/stm32l4x5/rcc/ccipr.rs

stm32l4/stm32l4x5/rcc/
ccipr.rs
