stm32l4/stm32l4x5/rcc/
apb2rstr.rs

1///Register `APB2RSTR` reader
2pub type R = crate::R<APB2RSTRrs>;
3///Register `APB2RSTR` writer
4pub type W = crate::W<APB2RSTRrs>;
5///Field `SYSCFGRST` reader - System configuration (SYSCFG) reset
6pub type SYSCFGRST_R = crate::BitReader;
7///Field `SYSCFGRST` writer - System configuration (SYSCFG) reset
8pub type SYSCFGRST_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `SDMMCRST` reader - SDMMC reset
10pub type SDMMCRST_R = crate::BitReader;
11///Field `SDMMCRST` writer - SDMMC reset
12pub type SDMMCRST_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `TIM1RST` reader - TIM1 timer reset
14pub type TIM1RST_R = crate::BitReader;
15///Field `TIM1RST` writer - TIM1 timer reset
16pub type TIM1RST_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `SPI1RST` reader - SPI1 reset
18pub type SPI1RST_R = crate::BitReader;
19///Field `SPI1RST` writer - SPI1 reset
20pub type SPI1RST_W<'a, REG> = crate::BitWriter<'a, REG>;
21///Field `TIM8RST` reader - TIM8 timer reset
22pub type TIM8RST_R = crate::BitReader;
23///Field `TIM8RST` writer - TIM8 timer reset
24pub type TIM8RST_W<'a, REG> = crate::BitWriter<'a, REG>;
25///Field `USART1RST` reader - USART1 reset
26pub type USART1RST_R = crate::BitReader;
27///Field `USART1RST` writer - USART1 reset
28pub type USART1RST_W<'a, REG> = crate::BitWriter<'a, REG>;
29///Field `TIM15RST` reader - TIM15 timer reset
30pub type TIM15RST_R = crate::BitReader;
31///Field `TIM15RST` writer - TIM15 timer reset
32pub type TIM15RST_W<'a, REG> = crate::BitWriter<'a, REG>;
33///Field `TIM16RST` reader - TIM16 timer reset
34pub type TIM16RST_R = crate::BitReader;
35///Field `TIM16RST` writer - TIM16 timer reset
36pub type TIM16RST_W<'a, REG> = crate::BitWriter<'a, REG>;
37///Field `TIM17RST` reader - TIM17 timer reset
38pub type TIM17RST_R = crate::BitReader;
39///Field `TIM17RST` writer - TIM17 timer reset
40pub type TIM17RST_W<'a, REG> = crate::BitWriter<'a, REG>;
41///Field `SAI1RST` reader - Serial audio interface 1 (SAI1) reset
42pub type SAI1RST_R = crate::BitReader;
43///Field `SAI1RST` writer - Serial audio interface 1 (SAI1) reset
44pub type SAI1RST_W<'a, REG> = crate::BitWriter<'a, REG>;
45///Field `SAI2RST` reader - Serial audio interface 2 (SAI2) reset
46pub type SAI2RST_R = crate::BitReader;
47///Field `SAI2RST` writer - Serial audio interface 2 (SAI2) reset
48pub type SAI2RST_W<'a, REG> = crate::BitWriter<'a, REG>;
49///Field `DFSDMRST` reader - Digital filters for sigma-delata modulators (DFSDM) reset
50pub type DFSDMRST_R = crate::BitReader;
51///Field `DFSDMRST` writer - Digital filters for sigma-delata modulators (DFSDM) reset
52pub type DFSDMRST_W<'a, REG> = crate::BitWriter<'a, REG>;
53impl R {
54    ///Bit 0 - System configuration (SYSCFG) reset
55    #[inline(always)]
56    pub fn syscfgrst(&self) -> SYSCFGRST_R {
57        SYSCFGRST_R::new((self.bits & 1) != 0)
58    }
59    ///Bit 10 - SDMMC reset
60    #[inline(always)]
61    pub fn sdmmcrst(&self) -> SDMMCRST_R {
62        SDMMCRST_R::new(((self.bits >> 10) & 1) != 0)
63    }
64    ///Bit 11 - TIM1 timer reset
65    #[inline(always)]
66    pub fn tim1rst(&self) -> TIM1RST_R {
67        TIM1RST_R::new(((self.bits >> 11) & 1) != 0)
68    }
69    ///Bit 12 - SPI1 reset
70    #[inline(always)]
71    pub fn spi1rst(&self) -> SPI1RST_R {
72        SPI1RST_R::new(((self.bits >> 12) & 1) != 0)
73    }
74    ///Bit 13 - TIM8 timer reset
75    #[inline(always)]
76    pub fn tim8rst(&self) -> TIM8RST_R {
77        TIM8RST_R::new(((self.bits >> 13) & 1) != 0)
78    }
79    ///Bit 14 - USART1 reset
80    #[inline(always)]
81    pub fn usart1rst(&self) -> USART1RST_R {
82        USART1RST_R::new(((self.bits >> 14) & 1) != 0)
83    }
84    ///Bit 16 - TIM15 timer reset
85    #[inline(always)]
86    pub fn tim15rst(&self) -> TIM15RST_R {
87        TIM15RST_R::new(((self.bits >> 16) & 1) != 0)
88    }
89    ///Bit 17 - TIM16 timer reset
90    #[inline(always)]
91    pub fn tim16rst(&self) -> TIM16RST_R {
92        TIM16RST_R::new(((self.bits >> 17) & 1) != 0)
93    }
94    ///Bit 18 - TIM17 timer reset
95    #[inline(always)]
96    pub fn tim17rst(&self) -> TIM17RST_R {
97        TIM17RST_R::new(((self.bits >> 18) & 1) != 0)
98    }
99    ///Bit 21 - Serial audio interface 1 (SAI1) reset
100    #[inline(always)]
101    pub fn sai1rst(&self) -> SAI1RST_R {
102        SAI1RST_R::new(((self.bits >> 21) & 1) != 0)
103    }
104    ///Bit 22 - Serial audio interface 2 (SAI2) reset
105    #[inline(always)]
106    pub fn sai2rst(&self) -> SAI2RST_R {
107        SAI2RST_R::new(((self.bits >> 22) & 1) != 0)
108    }
109    ///Bit 24 - Digital filters for sigma-delata modulators (DFSDM) reset
110    #[inline(always)]
111    pub fn dfsdmrst(&self) -> DFSDMRST_R {
112        DFSDMRST_R::new(((self.bits >> 24) & 1) != 0)
113    }
114}
115impl core::fmt::Debug for R {
116    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
117        f.debug_struct("APB2RSTR")
118            .field("dfsdmrst", &self.dfsdmrst())
119            .field("sai2rst", &self.sai2rst())
120            .field("sai1rst", &self.sai1rst())
121            .field("tim17rst", &self.tim17rst())
122            .field("tim16rst", &self.tim16rst())
123            .field("tim15rst", &self.tim15rst())
124            .field("usart1rst", &self.usart1rst())
125            .field("tim8rst", &self.tim8rst())
126            .field("spi1rst", &self.spi1rst())
127            .field("tim1rst", &self.tim1rst())
128            .field("sdmmcrst", &self.sdmmcrst())
129            .field("syscfgrst", &self.syscfgrst())
130            .finish()
131    }
132}
133impl W {
134    ///Bit 0 - System configuration (SYSCFG) reset
135    #[inline(always)]
136    pub fn syscfgrst(&mut self) -> SYSCFGRST_W<APB2RSTRrs> {
137        SYSCFGRST_W::new(self, 0)
138    }
139    ///Bit 10 - SDMMC reset
140    #[inline(always)]
141    pub fn sdmmcrst(&mut self) -> SDMMCRST_W<APB2RSTRrs> {
142        SDMMCRST_W::new(self, 10)
143    }
144    ///Bit 11 - TIM1 timer reset
145    #[inline(always)]
146    pub fn tim1rst(&mut self) -> TIM1RST_W<APB2RSTRrs> {
147        TIM1RST_W::new(self, 11)
148    }
149    ///Bit 12 - SPI1 reset
150    #[inline(always)]
151    pub fn spi1rst(&mut self) -> SPI1RST_W<APB2RSTRrs> {
152        SPI1RST_W::new(self, 12)
153    }
154    ///Bit 13 - TIM8 timer reset
155    #[inline(always)]
156    pub fn tim8rst(&mut self) -> TIM8RST_W<APB2RSTRrs> {
157        TIM8RST_W::new(self, 13)
158    }
159    ///Bit 14 - USART1 reset
160    #[inline(always)]
161    pub fn usart1rst(&mut self) -> USART1RST_W<APB2RSTRrs> {
162        USART1RST_W::new(self, 14)
163    }
164    ///Bit 16 - TIM15 timer reset
165    #[inline(always)]
166    pub fn tim15rst(&mut self) -> TIM15RST_W<APB2RSTRrs> {
167        TIM15RST_W::new(self, 16)
168    }
169    ///Bit 17 - TIM16 timer reset
170    #[inline(always)]
171    pub fn tim16rst(&mut self) -> TIM16RST_W<APB2RSTRrs> {
172        TIM16RST_W::new(self, 17)
173    }
174    ///Bit 18 - TIM17 timer reset
175    #[inline(always)]
176    pub fn tim17rst(&mut self) -> TIM17RST_W<APB2RSTRrs> {
177        TIM17RST_W::new(self, 18)
178    }
179    ///Bit 21 - Serial audio interface 1 (SAI1) reset
180    #[inline(always)]
181    pub fn sai1rst(&mut self) -> SAI1RST_W<APB2RSTRrs> {
182        SAI1RST_W::new(self, 21)
183    }
184    ///Bit 22 - Serial audio interface 2 (SAI2) reset
185    #[inline(always)]
186    pub fn sai2rst(&mut self) -> SAI2RST_W<APB2RSTRrs> {
187        SAI2RST_W::new(self, 22)
188    }
189    ///Bit 24 - Digital filters for sigma-delata modulators (DFSDM) reset
190    #[inline(always)]
191    pub fn dfsdmrst(&mut self) -> DFSDMRST_W<APB2RSTRrs> {
192        DFSDMRST_W::new(self, 24)
193    }
194}
195/**APB2 peripheral reset register
196
197You can [`read`](crate::Reg::read) this register and get [`apb2rstr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb2rstr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
198
199See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x5.html#RCC:APB2RSTR)*/
200pub struct APB2RSTRrs;
201impl crate::RegisterSpec for APB2RSTRrs {
202    type Ux = u32;
203}
204///`read()` method returns [`apb2rstr::R`](R) reader structure
205impl crate::Readable for APB2RSTRrs {}
206///`write(|w| ..)` method takes [`apb2rstr::W`](W) writer structure
207impl crate::Writable for APB2RSTRrs {
208    type Safety = crate::Unsafe;
209}
210///`reset()` method sets APB2RSTR to value 0
211impl crate::Resettable for APB2RSTRrs {}
stm32l4/stm32l4x5/rcc/apb2rstr.rs

stm32l4/stm32l4x5/rcc/
apb2rstr.rs
