stm32l4/stm32l4x5/rcc/
apb1rstr2.rs

1///Register `APB1RSTR2` reader
2pub type R = crate::R<APB1RSTR2rs>;
3///Register `APB1RSTR2` writer
4pub type W = crate::W<APB1RSTR2rs>;
5///Field `LPUART1RST` reader - Low-power UART 1 reset
6pub type LPUART1RST_R = crate::BitReader;
7///Field `LPUART1RST` writer - Low-power UART 1 reset
8pub type LPUART1RST_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `SWPMI1RST` reader - Single wire protocol reset
10pub type SWPMI1RST_R = crate::BitReader;
11///Field `SWPMI1RST` writer - Single wire protocol reset
12pub type SWPMI1RST_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `LPTIM2RST` reader - Low-power timer 2 reset
14pub type LPTIM2RST_R = crate::BitReader;
15///Field `LPTIM2RST` writer - Low-power timer 2 reset
16pub type LPTIM2RST_W<'a, REG> = crate::BitWriter<'a, REG>;
17impl R {
18    ///Bit 0 - Low-power UART 1 reset
19    #[inline(always)]
20    pub fn lpuart1rst(&self) -> LPUART1RST_R {
21        LPUART1RST_R::new((self.bits & 1) != 0)
22    }
23    ///Bit 2 - Single wire protocol reset
24    #[inline(always)]
25    pub fn swpmi1rst(&self) -> SWPMI1RST_R {
26        SWPMI1RST_R::new(((self.bits >> 2) & 1) != 0)
27    }
28    ///Bit 5 - Low-power timer 2 reset
29    #[inline(always)]
30    pub fn lptim2rst(&self) -> LPTIM2RST_R {
31        LPTIM2RST_R::new(((self.bits >> 5) & 1) != 0)
32    }
33}
34impl core::fmt::Debug for R {
35    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
36        f.debug_struct("APB1RSTR2")
37            .field("lptim2rst", &self.lptim2rst())
38            .field("swpmi1rst", &self.swpmi1rst())
39            .field("lpuart1rst", &self.lpuart1rst())
40            .finish()
41    }
42}
43impl W {
44    ///Bit 0 - Low-power UART 1 reset
45    #[inline(always)]
46    pub fn lpuart1rst(&mut self) -> LPUART1RST_W<APB1RSTR2rs> {
47        LPUART1RST_W::new(self, 0)
48    }
49    ///Bit 2 - Single wire protocol reset
50    #[inline(always)]
51    pub fn swpmi1rst(&mut self) -> SWPMI1RST_W<APB1RSTR2rs> {
52        SWPMI1RST_W::new(self, 2)
53    }
54    ///Bit 5 - Low-power timer 2 reset
55    #[inline(always)]
56    pub fn lptim2rst(&mut self) -> LPTIM2RST_W<APB1RSTR2rs> {
57        LPTIM2RST_W::new(self, 5)
58    }
59}
60/**APB1 peripheral reset register 2
61
62You can [`read`](crate::Reg::read) this register and get [`apb1rstr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb1rstr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
63
64See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x5.html#RCC:APB1RSTR2)*/
65pub struct APB1RSTR2rs;
66impl crate::RegisterSpec for APB1RSTR2rs {
67    type Ux = u32;
68}
69///`read()` method returns [`apb1rstr2::R`](R) reader structure
70impl crate::Readable for APB1RSTR2rs {}
71///`write(|w| ..)` method takes [`apb1rstr2::W`](W) writer structure
72impl crate::Writable for APB1RSTR2rs {
73    type Safety = crate::Unsafe;
74}
75///`reset()` method sets APB1RSTR2 to value 0
76impl crate::Resettable for APB1RSTR2rs {}
stm32l4/stm32l4x5/rcc/apb1rstr2.rs

stm32l4/stm32l4x5/rcc/
apb1rstr2.rs
