stm32l4/stm32l4x5/rcc/
ahb3smenr.rs

1///Register `AHB3SMENR` reader
2pub type R = crate::R<AHB3SMENRrs>;
3///Register `AHB3SMENR` writer
4pub type W = crate::W<AHB3SMENRrs>;
5///Field `FMCSMEN` reader - Flexible memory controller clocks enable during Sleep and Stop modes
6pub type FMCSMEN_R = crate::BitReader;
7///Field `FMCSMEN` writer - Flexible memory controller clocks enable during Sleep and Stop modes
8pub type FMCSMEN_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `QSPISMEN` reader - QSPISMEN
10pub type QSPISMEN_R = crate::BitReader;
11///Field `QSPISMEN` writer - QSPISMEN
12pub type QSPISMEN_W<'a, REG> = crate::BitWriter<'a, REG>;
13impl R {
14    ///Bit 0 - Flexible memory controller clocks enable during Sleep and Stop modes
15    #[inline(always)]
16    pub fn fmcsmen(&self) -> FMCSMEN_R {
17        FMCSMEN_R::new((self.bits & 1) != 0)
18    }
19    ///Bit 8 - QSPISMEN
20    #[inline(always)]
21    pub fn qspismen(&self) -> QSPISMEN_R {
22        QSPISMEN_R::new(((self.bits >> 8) & 1) != 0)
23    }
24}
25impl core::fmt::Debug for R {
26    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
27        f.debug_struct("AHB3SMENR")
28            .field("qspismen", &self.qspismen())
29            .field("fmcsmen", &self.fmcsmen())
30            .finish()
31    }
32}
33impl W {
34    ///Bit 0 - Flexible memory controller clocks enable during Sleep and Stop modes
35    #[inline(always)]
36    pub fn fmcsmen(&mut self) -> FMCSMEN_W<AHB3SMENRrs> {
37        FMCSMEN_W::new(self, 0)
38    }
39    ///Bit 8 - QSPISMEN
40    #[inline(always)]
41    pub fn qspismen(&mut self) -> QSPISMEN_W<AHB3SMENRrs> {
42        QSPISMEN_W::new(self, 8)
43    }
44}
45/**AHB3 peripheral clocks enable in Sleep and Stop modes register
46
47You can [`read`](crate::Reg::read) this register and get [`ahb3smenr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahb3smenr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
48
49See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x5.html#RCC:AHB3SMENR)*/
50pub struct AHB3SMENRrs;
51impl crate::RegisterSpec for AHB3SMENRrs {
52    type Ux = u32;
53}
54///`read()` method returns [`ahb3smenr::R`](R) reader structure
55impl crate::Readable for AHB3SMENRrs {}
56///`write(|w| ..)` method takes [`ahb3smenr::W`](W) writer structure
57impl crate::Writable for AHB3SMENRrs {
58    type Safety = crate::Unsafe;
59}
60///`reset()` method sets AHB3SMENR to value 0x0101
61impl crate::Resettable for AHB3SMENRrs {
62    const RESET_VALUE: u32 = 0x0101;
63}
stm32l4/stm32l4x5/rcc/ahb3smenr.rs

stm32l4/stm32l4x5/rcc/
ahb3smenr.rs
