stm32l4/stm32l4x5/rcc/
ahb2enr.rs

1///Register `AHB2ENR` reader
2pub type R = crate::R<AHB2ENRrs>;
3///Register `AHB2ENR` writer
4pub type W = crate::W<AHB2ENRrs>;
5///Field `GPIOAEN` reader - IO port A clock enable
6pub type GPIOAEN_R = crate::BitReader;
7///Field `GPIOAEN` writer - IO port A clock enable
8pub type GPIOAEN_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `GPIOBEN` reader - IO port B clock enable
10pub type GPIOBEN_R = crate::BitReader;
11///Field `GPIOBEN` writer - IO port B clock enable
12pub type GPIOBEN_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `GPIOCEN` reader - IO port C clock enable
14pub type GPIOCEN_R = crate::BitReader;
15///Field `GPIOCEN` writer - IO port C clock enable
16pub type GPIOCEN_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `GPIODEN` reader - IO port D clock enable
18pub type GPIODEN_R = crate::BitReader;
19///Field `GPIODEN` writer - IO port D clock enable
20pub type GPIODEN_W<'a, REG> = crate::BitWriter<'a, REG>;
21///Field `GPIOEEN` reader - IO port E clock enable
22pub type GPIOEEN_R = crate::BitReader;
23///Field `GPIOEEN` writer - IO port E clock enable
24pub type GPIOEEN_W<'a, REG> = crate::BitWriter<'a, REG>;
25///Field `GPIOFEN` reader - IO port F clock enable
26pub type GPIOFEN_R = crate::BitReader;
27///Field `GPIOFEN` writer - IO port F clock enable
28pub type GPIOFEN_W<'a, REG> = crate::BitWriter<'a, REG>;
29///Field `GPIOGEN` reader - IO port G clock enable
30pub type GPIOGEN_R = crate::BitReader;
31///Field `GPIOGEN` writer - IO port G clock enable
32pub type GPIOGEN_W<'a, REG> = crate::BitWriter<'a, REG>;
33///Field `GPIOHEN` reader - IO port H clock enable
34pub type GPIOHEN_R = crate::BitReader;
35///Field `GPIOHEN` writer - IO port H clock enable
36pub type GPIOHEN_W<'a, REG> = crate::BitWriter<'a, REG>;
37///Field `OTGFSEN` reader - OTG full speed clock enable
38pub type OTGFSEN_R = crate::BitReader;
39///Field `OTGFSEN` writer - OTG full speed clock enable
40pub type OTGFSEN_W<'a, REG> = crate::BitWriter<'a, REG>;
41/**ADC clock enable
42
43Value on reset: 0*/
44#[cfg_attr(feature = "defmt", derive(defmt::Format))]
45#[derive(Clone, Copy, Debug, PartialEq, Eq)]
46pub enum ADCEN {
47    ///0: ADC clock disabled
48    Disabled = 0,
49    ///1: ADC clock enabled
50    Enabled = 1,
51}
52impl From<ADCEN> for bool {
53    #[inline(always)]
54    fn from(variant: ADCEN) -> Self {
55        variant as u8 != 0
56    }
57}
58///Field `ADCEN` reader - ADC clock enable
59pub type ADCEN_R = crate::BitReader<ADCEN>;
60impl ADCEN_R {
61    ///Get enumerated values variant
62    #[inline(always)]
63    pub const fn variant(&self) -> ADCEN {
64        match self.bits {
65            false => ADCEN::Disabled,
66            true => ADCEN::Enabled,
67        }
68    }
69    ///ADC clock disabled
70    #[inline(always)]
71    pub fn is_disabled(&self) -> bool {
72        *self == ADCEN::Disabled
73    }
74    ///ADC clock enabled
75    #[inline(always)]
76    pub fn is_enabled(&self) -> bool {
77        *self == ADCEN::Enabled
78    }
79}
80///Field `ADCEN` writer - ADC clock enable
81pub type ADCEN_W<'a, REG> = crate::BitWriter<'a, REG, ADCEN>;
82impl<'a, REG> ADCEN_W<'a, REG>
83where
84    REG: crate::Writable + crate::RegisterSpec,
85{
86    ///ADC clock disabled
87    #[inline(always)]
88    pub fn disabled(self) -> &'a mut crate::W<REG> {
89        self.variant(ADCEN::Disabled)
90    }
91    ///ADC clock enabled
92    #[inline(always)]
93    pub fn enabled(self) -> &'a mut crate::W<REG> {
94        self.variant(ADCEN::Enabled)
95    }
96}
97///Field `AESEN` reader - AES accelerator clock enable
98pub type AESEN_R = crate::BitReader;
99///Field `AESEN` writer - AES accelerator clock enable
100pub type AESEN_W<'a, REG> = crate::BitWriter<'a, REG>;
101///Field `RNGEN` reader - Random Number Generator clock enable
102pub type RNGEN_R = crate::BitReader;
103///Field `RNGEN` writer - Random Number Generator clock enable
104pub type RNGEN_W<'a, REG> = crate::BitWriter<'a, REG>;
105impl R {
106    ///Bit 0 - IO port A clock enable
107    #[inline(always)]
108    pub fn gpioaen(&self) -> GPIOAEN_R {
109        GPIOAEN_R::new((self.bits & 1) != 0)
110    }
111    ///Bit 1 - IO port B clock enable
112    #[inline(always)]
113    pub fn gpioben(&self) -> GPIOBEN_R {
114        GPIOBEN_R::new(((self.bits >> 1) & 1) != 0)
115    }
116    ///Bit 2 - IO port C clock enable
117    #[inline(always)]
118    pub fn gpiocen(&self) -> GPIOCEN_R {
119        GPIOCEN_R::new(((self.bits >> 2) & 1) != 0)
120    }
121    ///Bit 3 - IO port D clock enable
122    #[inline(always)]
123    pub fn gpioden(&self) -> GPIODEN_R {
124        GPIODEN_R::new(((self.bits >> 3) & 1) != 0)
125    }
126    ///Bit 4 - IO port E clock enable
127    #[inline(always)]
128    pub fn gpioeen(&self) -> GPIOEEN_R {
129        GPIOEEN_R::new(((self.bits >> 4) & 1) != 0)
130    }
131    ///Bit 5 - IO port F clock enable
132    #[inline(always)]
133    pub fn gpiofen(&self) -> GPIOFEN_R {
134        GPIOFEN_R::new(((self.bits >> 5) & 1) != 0)
135    }
136    ///Bit 6 - IO port G clock enable
137    #[inline(always)]
138    pub fn gpiogen(&self) -> GPIOGEN_R {
139        GPIOGEN_R::new(((self.bits >> 6) & 1) != 0)
140    }
141    ///Bit 7 - IO port H clock enable
142    #[inline(always)]
143    pub fn gpiohen(&self) -> GPIOHEN_R {
144        GPIOHEN_R::new(((self.bits >> 7) & 1) != 0)
145    }
146    ///Bit 12 - OTG full speed clock enable
147    #[inline(always)]
148    pub fn otgfsen(&self) -> OTGFSEN_R {
149        OTGFSEN_R::new(((self.bits >> 12) & 1) != 0)
150    }
151    ///Bit 13 - ADC clock enable
152    #[inline(always)]
153    pub fn adcen(&self) -> ADCEN_R {
154        ADCEN_R::new(((self.bits >> 13) & 1) != 0)
155    }
156    ///Bit 16 - AES accelerator clock enable
157    #[inline(always)]
158    pub fn aesen(&self) -> AESEN_R {
159        AESEN_R::new(((self.bits >> 16) & 1) != 0)
160    }
161    ///Bit 18 - Random Number Generator clock enable
162    #[inline(always)]
163    pub fn rngen(&self) -> RNGEN_R {
164        RNGEN_R::new(((self.bits >> 18) & 1) != 0)
165    }
166}
167impl core::fmt::Debug for R {
168    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
169        f.debug_struct("AHB2ENR")
170            .field("rngen", &self.rngen())
171            .field("aesen", &self.aesen())
172            .field("adcen", &self.adcen())
173            .field("otgfsen", &self.otgfsen())
174            .field("gpiohen", &self.gpiohen())
175            .field("gpiogen", &self.gpiogen())
176            .field("gpiofen", &self.gpiofen())
177            .field("gpioeen", &self.gpioeen())
178            .field("gpioden", &self.gpioden())
179            .field("gpiocen", &self.gpiocen())
180            .field("gpioben", &self.gpioben())
181            .field("gpioaen", &self.gpioaen())
182            .finish()
183    }
184}
185impl W {
186    ///Bit 0 - IO port A clock enable
187    #[inline(always)]
188    pub fn gpioaen(&mut self) -> GPIOAEN_W<AHB2ENRrs> {
189        GPIOAEN_W::new(self, 0)
190    }
191    ///Bit 1 - IO port B clock enable
192    #[inline(always)]
193    pub fn gpioben(&mut self) -> GPIOBEN_W<AHB2ENRrs> {
194        GPIOBEN_W::new(self, 1)
195    }
196    ///Bit 2 - IO port C clock enable
197    #[inline(always)]
198    pub fn gpiocen(&mut self) -> GPIOCEN_W<AHB2ENRrs> {
199        GPIOCEN_W::new(self, 2)
200    }
201    ///Bit 3 - IO port D clock enable
202    #[inline(always)]
203    pub fn gpioden(&mut self) -> GPIODEN_W<AHB2ENRrs> {
204        GPIODEN_W::new(self, 3)
205    }
206    ///Bit 4 - IO port E clock enable
207    #[inline(always)]
208    pub fn gpioeen(&mut self) -> GPIOEEN_W<AHB2ENRrs> {
209        GPIOEEN_W::new(self, 4)
210    }
211    ///Bit 5 - IO port F clock enable
212    #[inline(always)]
213    pub fn gpiofen(&mut self) -> GPIOFEN_W<AHB2ENRrs> {
214        GPIOFEN_W::new(self, 5)
215    }
216    ///Bit 6 - IO port G clock enable
217    #[inline(always)]
218    pub fn gpiogen(&mut self) -> GPIOGEN_W<AHB2ENRrs> {
219        GPIOGEN_W::new(self, 6)
220    }
221    ///Bit 7 - IO port H clock enable
222    #[inline(always)]
223    pub fn gpiohen(&mut self) -> GPIOHEN_W<AHB2ENRrs> {
224        GPIOHEN_W::new(self, 7)
225    }
226    ///Bit 12 - OTG full speed clock enable
227    #[inline(always)]
228    pub fn otgfsen(&mut self) -> OTGFSEN_W<AHB2ENRrs> {
229        OTGFSEN_W::new(self, 12)
230    }
231    ///Bit 13 - ADC clock enable
232    #[inline(always)]
233    pub fn adcen(&mut self) -> ADCEN_W<AHB2ENRrs> {
234        ADCEN_W::new(self, 13)
235    }
236    ///Bit 16 - AES accelerator clock enable
237    #[inline(always)]
238    pub fn aesen(&mut self) -> AESEN_W<AHB2ENRrs> {
239        AESEN_W::new(self, 16)
240    }
241    ///Bit 18 - Random Number Generator clock enable
242    #[inline(always)]
243    pub fn rngen(&mut self) -> RNGEN_W<AHB2ENRrs> {
244        RNGEN_W::new(self, 18)
245    }
246}
247/**AHB2 peripheral clock enable register
248
249You can [`read`](crate::Reg::read) this register and get [`ahb2enr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahb2enr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
250
251See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x5.html#RCC:AHB2ENR)*/
252pub struct AHB2ENRrs;
253impl crate::RegisterSpec for AHB2ENRrs {
254    type Ux = u32;
255}
256///`read()` method returns [`ahb2enr::R`](R) reader structure
257impl crate::Readable for AHB2ENRrs {}
258///`write(|w| ..)` method takes [`ahb2enr::W`](W) writer structure
259impl crate::Writable for AHB2ENRrs {
260    type Safety = crate::Unsafe;
261}
262///`reset()` method sets AHB2ENR to value 0
263impl crate::Resettable for AHB2ENRrs {}
stm32l4/stm32l4x5/rcc/ahb2enr.rs

stm32l4/stm32l4x5/rcc/
ahb2enr.rs
